Senior Silicon Product Engineer - Manufacturing

NVIDIA Corporation; United States; Hybrid; USD 168,000 - 265,000; Full time

Benefits offered by this job

Hybrid work option

Job summary

NVIDIA Corporation’s Silicon Co-Design Group is seeking a senior engineer to drive SLT testability and coverage for high-volume manufacturing of SoCs/GPUs/CPUs. You will partner across hardware, software, and platform teams to optimize test flows from silicon bring-up to production.

We value hands-on lab experience, strong data analytics, and a track record of ownership of manufacturing test strategies in a large-scale device environment.

Qualifications

• 8+ years in silicon Post-silicon PVT validation or high-volume manufacturing testing.
• Hands-on lab bring-up, debugging, and data correlation to Si characterization.
• Strong EE fundamentals and knowledge of silicon design and stats.

Responsibilities

• Partner with HW/SW teams to determine test content and SLT conditions.
• Improve SLT testing infrastructure, knobs, and data collection.
• Co-design SLT scope, enhance coverage, and optimize test flows for manufacturing.
• Prototype speed/power/ yield improvements; correlate to design.
• Define silicon correlation procedures between production testing and diagnostics.
• Support escalations with customer-facing and quality teams; close gaps in coverage.
• Drive manufacturability, test-time reduction, and cost vs. coverage tradeoffs.
• Lead process improvements through root-cause analysis and data analytics.

Skills

Post-silicon PVT validation

High-volume manufacturing testing

Data analysis

Python

Bash

Linux

Lab debugging

Cross-functional leadership

Education

Bachelor's or Master's in Microelectronics/Electrical/Electronic/CS

Tools

Python

Bash

Linux

Job description

NVIDIA's Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first-principles thinking and engineering judgment at the highest level translate directly into product outcomes at scale. Our team gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production!

What you will be doing:

• Partner multi-functionally with HW engineering teams such as Silicon PVT design and characterization teams, IO design and validation teams, system feature owners, SLT and BLT Production Operations, etc., to determine test coverage and constraints to resolve appropriate SLT test conditions, test content, and flows for high-volume manufacturing screens.
• Partner with SW and platform teams to support and improve SLT testing infrastructure, debug knobs, and data collection features needed to support manufacturing screens effectively.
• Co-design SLT testability scope and coverage enhancements for Nvidia's manufacturing testing with a focus on high-volume system-level manufacturing screens.
• Prototype and fine-tune speed, power, circuits, yield, and quality for effective silicon coverage in the SLT socketed environment.
• Co-design, develop, and maintain SLT testing flows and incorporate takeaways from silicon and correlate to design.
• Define procedures to facilitate Silicon correlation activities between production testing infrastructure and internal Si characterization and diagnostics programs.
• Support customer-facing and quality teams during customer escalations to understand the issues and fix gaps identified in SLT production coverage.
• Drive alignment for manufacturability, test time optimization and reduction, cost vs. coverage tradeoffs, etc., to evaluate the effectiveness of new tests.
• Initiate and drive process improvements and preventative actions through root cause analysis and data analytics.

What we need to see:

• Bachelor's or Master's Degree or equivalent in Microelectronics/Electrical/Electronic/Computer Engineering or equivalent experience.
• 8+ years of relevant proven experience in silicon Post-silicon PVT validation and/or High-volume manufacturing testing for sophisticated SoCs, GPUs, CPUs, or similar.
• Hands-on lab experience with silicon bring-up, lab debug, test content bring-up, and correlation to Si characterization, yield, and coverage optimization.
• Strong EE fundamentals, device physics, knowledgeable in Silicon design, statistics, STA concepts, signal integrity, fault analysis, sampling, and computer architecture.
• Excellent interpersonal skills and demonstrated ability to drive multi-functional alignment around plans, dependencies, and sign-off criteria.
• Prior ownership of manufacturing test strategy for a major silicon product (e.g., GPU/SoC/CPU) from early planning through ramp to QS/production.
• Strong data analysis skills. Prior experience working with volume data is a plus.
• Good understanding of firmware/driver structures and their interaction with HW.
• Problem-solving, debugging, analysis, and logical reasoning skills with examples to prove it.
• Experience with Python, BASH, Linux, and scripting.

Ways to stand out above the crowd:

• Outstanding work ethic and up-leveling discussions to solve the real problems
• Native use of AI tools to accelerate production testing and debug workflows
• Battle-tested on GPUs, CPUs, AI accelerators, or other large-scale SoCs - you've seen firsthand how complexity at scale reshapes the failure landscape and demands a different level of engineering intuition.
• Co-designed or led multi-functional alignment on production methodologies adopted by other teams in a High Volume Manufacturing(HVM) environment.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310