Senior Silicon Failure Analysis Engineer – DFT/Scan Debug

Intel Corporation; Hillsboro (OR); Hybrid; USD 142.000 - 269.000; Vollzeit

Benefits dieser Stelle

Competitive pay

Stock bonuses

Health benefits

Zusammenfassung

Intel Corporation’s Oregon Hillsboro campus is seeking an experienced Product Failure Analysis Engineer - SCAN Design for Test to accelerate the ramp and quality of Foundry 18A technology. You will lead root-cause analysis of silicon failures and collaborate across design, test, and manufacturing teams.

The role requires hands-on experience with ATPG, scan diagnosis, and physical failure analysis methods (FIB/SEM/TEM) and a passion for developing innovative diagnostic frameworks to improve debug

Qualifikationen

• Bachelor’s degree in electrical engineering, computer engineering, or a related STEM discipline with 6+ years of hands‑on experience; or master’s with 4+ years; or PhD with 2+ years.
• Hands–on experience with DFT tools/techniques, SCAN ATPG, and Scan Chain Diagnosis.
• Experience with fault isolation techniques including ATPG pattern generation, fault modeling, and Scan architecture.
• Experience with debugging silicon issues on leading‑edge technology nodes.
• Experience developing debug automation and analysis tools using Python, Perl, or TCL.

Aufgaben

• Lead Failure Analysis using lab equipment to isolate silicon failures and identify root causes with precision.
• Drive cross-functional collaboration with test, validation, circuit design, and manufacturing teams to resolve quality issues.
• Advance debug technologies by developing new tools and methodologies for silicon debugging.
• Ensure design for debug features are incorporated to enable deep silicon isolation capabilities.
• Support continuous improvement through investigations and design process enhancements.

Kenntnisse

DFT architectures

ATPG

Scan diagnosis

Fault modeling

Python scripting

Ausbildung

Bachelor’s degree in electrical engineering, computer engineering or related STEM

Master’s degree or PhD (optional)

Tools

Siemens Tessent

TetraMAX

Verdi

DVE

Python

Perl

TCL

Jobbeschreibung

Intel Corporation’s Oregon Hillsboro campus is seeking an experienced Product Failure Analysis Engineer - SCAN Design for Test to accelerate the ramp and quality of Foundry 18A technology. You will lead root-cause analysis of silicon failures and collaborate across design, test, and manufacturing teams.

The role requires hands-on experience with ATPG, scan diagnosis, and physical failure analysis methods (FIB/SEM/TEM) and a passion for developing innovative diagnostic frameworks to improve debug