Senior RTL Design Engineer

sambanovasystems; Austin (TX); On-site; USD 120,000 - 200,000; Full time

Benefits offered by this job

Health insurance

Employer 401(k) with match

On-site health and wellness

Job summary

SambaNova Systems is seeking an RTL Design Engineer to contribute to a Reconfigurable Dataflow Unit (RDU) ASIC family. You will implement SystemVerilog, verify logic, and help optimize power, performance, and area.

The role collaborates with principal engineers and design teams across tape-out and silicon bring-up. Requirements include a BS in a related field and 5+ years in ASIC RTL design, with strong knowledge of interconnects, SPICE‑level timing, and SV assertions.

Qualifications

• BS degree in EE/CE/CS or equivalent; advanced degrees preferred.
• 5+ years of ASIC RTL design experience with SystemVerilog.
• Strong fundamentals in architecture and digital logic.

Responsibilities

• Own blocks within a larger RTL subsystem and contribute to microarchitecture specs.
• Write and debug RTL; carry blocks through implementation, tape-out, and silicon bring-up.
• Collaborate with engineers across verification, design, and physical teams.

Skills

SystemVerilog RTL design

digital logic design

computer architecture

interconnect protocols (AXI, PCIe, Eth

timing analysis

linting/clock domain crossing

logical equivalence checking

Git

Python scripting

Linux shell

Education

B.S. in Electrical Engineering, Computer Engineering, or Computer Science

M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Synthesis tools

Static timing analysis

linting tools

clock domain crossing checks

HDL verification tools

Job description

The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale.

SambaNova Suite™ is the first full‑stack, generative AI platform, from chip to model, optimized for enterprise and government organizations. Powered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on‑premises or in the cloud, combined with state‑of‑the‑art open‑source models that can be easily and securely fine‑tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so they can turn generative AI into one of their most valuable assets.

The RTL design team builds the compute datapath, on‑chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape‑out: RTL implementation, PPA trade‑offs, quality gates like lint, CDC, and LEC, and timing closure with

SambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape‑out, and silicon bring‑up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture

Required Qualifications

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science
• 5+ years of experience in ASIC RTL design
• Solid foundation in computer architecture and digital logic design
• Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
• Experience making design decisions that trade off power, performance, and area
• Knowledge of industry‑standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
• Experience with digital logic synthesis tools and static timing analysis
• Proficiency with industry‑standard tools for linting, clock domain crossing, and logical equivalence checking
• Experience implementing SystemVerilog Assertions to check design intent
• Familiarity with tools and simulators for hardware performance analysis and tuning
• Familiarity with Git for managing release cycles
• Scripting skills in Python and Linux shell

Preferred Qualifications

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
• Exposure to a full ASIC development cycle through tape‑out and production silicon
• Interest in or knowledge of AI workload acceleration techniques
• Experience with low‑power design techniques such as clock gating and DVFS at advanced process nodes
• Exposure to emulation or FPGA prototyping platforms for pre‑silicon validation

Base Salary Range:

Base Pay Range $120,000 - $200,000 USD

EEO Policy

SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions

SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well‑being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.