Senior RTL Design Engineer

SambaNova; Austin (TX); On-site; USD 120,000 - 200,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

Disability insurance

Life insurance

AD&D insurance

HSA contributions

FSA options

Headspace access

Gympass+

One Medical

Counseling services (EAP)

EAP access

Job summary

SambaNova Systems is seeking an experienced RTL Design Engineer to own blocks within an RDU ASIC subsystem. You will contribute to microarchitecture, write and debug SystemVerilog, and guide blocks through implementation, tape-out, and silicon bring-up in collaboration with verification and physical design teams.

The role requires strong SystemVerilog skills, a solid digital logic foundation, and experience with power, performance, and area trade-offs on high-speed ASICs.

Qualifications

• BS in EE, CE, or CS required.
• 5+ years of ASIC RTL design experience.
• Strong digital logic and computer architecture knowledge.
• SystemVerilog for high-speed ASICs with power/performance/area trade-offs.
• Experience with AXI, PCIe, Ethernet, and HBM or DDR.
• Proficient with RTL Synthesis, Lint, CDC, and STA workflows.

Responsibilities

• Own blocks within a larger RTL subsystem and contribute to microarchitecture specs.
• Write and debug RTL and carry blocks through implementation and tape-out.
• Collaborate with design verification, physical design, and architecture teams.
• Participate in silicon bring-up and performance tuning.

Skills

ASIC RTL design

SystemVerilog

Power/Performance/Area trade-offs

Computer architecture

Digital logic design

Interconnect protocols

Linting & CDC

SystemVerilog Assertions

Hardware performance analysis

Git

Python & Linux shell

Education

B.S. in Electrical Engineering / Computer Engineering / Computer Science

MS or PhD in EE/CE/CS

Tools

Synthesis tools

Static timing analysis tools

RTL simulators

Linting tools

Job description

About the team About the role

The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out: RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with

About the role

SambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape-out, and silicon bring-up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture

Required Qualifications

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science
• 5+ years of experience in ASIC RTL design
• Solid foundation in computer architecture and digital logic design
• Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
• Experience making design decisions that trade off power, performance, and area
• Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
• Experience with digital logic synthesis tools and static timing analysisProficiency with industry-standard tools for linting, clock domain crossing, and logical equivalence checking
• Experience implementing SystemVerilog Assertions to check design intent
• Familiarity with tools and simulators for hardware performance analysis and tuning
• Familiarity with Git for managing release cycles
• Scripting skills in Python and Linux shell

Preferred Qualifications

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
• Exposure to a full ASIC development cycle through tape-out and production silicon
• Interest in or knowledge of AI workload acceleration techniques
• Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes
• Exposure to emulation or FPGA prototyping platforms for pre-silicon validation

Base Salary Range:

Base Pay Range

$120,000 — $200,000 USD

EEO Policy

SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions

SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.