Senior RF Test & PCB Design Engineer

Prodapt; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Prodapt seeks a Senior RF Test & PCB Design Engineer in San Jose, CA for a 5 days onsite role. You will lead RF PCB layout, perform SI/PI simulations, and drive board bring-up and testing with lab equipment to validate design performance.

Responsibilities include RF characterization, impedance matching, and cross-functional collaboration with RFIC and System Engineering teams. Requires 5+ years in RF PCB design andCadence HFSS proficiency.

Qualifications

• Extensive PCB layout and high-frequency board design experience.
• Experience with Cadence Allegro/OrCAD for RF boards is required.
• Knowledge of SI/PI and EM simulations is essential.

Responsibilities

• Lead schematic entry, component selection, and RF board layout optimization.
• Perform SI/PI simulations and EM modeling for impedance matching.
• Own board bring-up, debugging, and validation against specs.
• Characterize RF performance with lab equipment and analyze data.

Skills

PCB layout

Cadence Allegro

RF engineering

EM simulations

ML for RF

Education

BS/MS in Electrical Engineering

Tools

Ansys HFSS

Job description

Prodapt ASIC Services (formerly Innovative Logic) provides end-to-end SoC/ASIC, FPGA, and embedded software solutions. Their design services cover the complete lifecycle from RTL to GDSII, covering domains like 3nm node physical design, UVM verification, DFT, and silicon bring-up for 5G, AI, and IoT.

We are looking for Senior RF Test & PCB Design Engineer in San Jose, CA and its a 5 days onsite position.

Responsibilities

• PCB Development: Lead the schematic entry, component selection, and layout routing optimization for complex RF evaluation boards using Cadence Allegro.
• Simulation & Analysis: Perform Signal Integrity (SI) and Power Integrity (PI) simulations. Utilize Ansys HFSS for EM modeling and impedance matching to ensure optimal RF performance.
• Hardware Bring-up: Own the board bring-up process, including debugging hardware issues and validating performance against design specifications.
• RF Characterization: Utilize lab equipment (VNAs, Spectrum Analyzers, Signal Generators) to perform various RF measurements and verify simulation-to-measurement correlations. Implement Machine Learning (ML) techniques to analyze large datasets and identify performance trends or anomalies.
• Cross-functional Collaboration: Work closely with RFIC Design and System Engineering teams to define board requirements and provide feedback on chip-level performance.
• Documentation & Data Analysis: Maintain detailed design documentations and test reports for internal and external stakeholders. Collect, review and analyze test data.
  Requirements

Must Haves

• Extensive actual PCB and layout design experience (not just as a reviewer) using Cadence Allegro/OrCAD tool. High speed or mmWave experience preferred.
• Materials Knowledge: Deep understanding of PCB stack-ups, dielectric materials (e.g., Rogers, Megtron), and manufacturing constraints for high-frequency PCB designs.
• Expertise in SI/PI and EM simulations.

Requirements

• Education: BS or MS in Electrical Engineering or a related technical field.
• Experience: 5+ years of hands-on experience in RF PCB design and hardware development.
• Tools: Expert-level proficiency in Cadence Allegro/OrCAD and Ansys HFSS (or equivalent EM simulation tools).
• RF Fundamentals: Strong knowledge of RF theory, including S-parameters, transmission line theory, matching networks, and de-embedding techniques.
• Lab Expertise: Extensive experience with RF test equipment (VNAs, Spectrum Analyzers, Oscilloscopes) and high-speed probing techniques.
• Materials Knowledge: Deep understanding of PCB stack-ups, dielectric materials (e.g., Rogers, Megtron), and manufacturing constraints for high-frequency PCB designs. Desirable Skills (Nice to Have)
• Automation: Proficiency in Python or C# for developing automated test suites to increase characterization throughput.
• Data Science for RF: Experience applying AI/ML models for predictive maintenance of test setups or for signal classification.
• Wafer-Level Testing: Experience with manual or semi-automated RF probe stations for on-wafer die characterization.