Senior RF/Analog ASIC Layout Engineer - Bonus Eligible

Systems Planning and Analysis, Inc.

Boulder (CO)

On-site

USD 104,000 - 192,000

Full time

14 days+

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Benefits offered by this job

Bonus eligible

Job summary

Tektronix is seeking an experienced ASIC Layout Design Engineer to perform block and chip-level layout of high-performance RF analog ASICs, collaborating with design engineers and layout teams. You will ensure smooth product flow from development to mass production, driving yield and test-time improvements.

The role requires 7+ years in RF/Analog/Mixed-Signal layout, proficiency with Cadence Virtuoso and PDKs across multiple foundries, and strong skills in layout planning, routing, and

Qualifications

7+ years in RF/Analog/Mixed-Signal layout design.
Strong understanding of RF, analog, digital routing and verification.
Experience with multiple foundries and PDKs.

Responsibilities

Layout of cells, blocks, and chips in CMOS, BiCMOS, and Bipolar processes.
Chip-level assembly, verification, and debugging.
Planning and managing layout teams, including contractors and teammates.
Layout tool development and training.
Troubleshooting layout software and PDKs; project database management.
Driving top-down abstraction and black-box methodology.

Skills

RF/Analog/Mixed-signal layout

High-speed RF layout

Mentoring / leadership

Layout planning / optimization

Python

Tools

Cadence Virtuoso Schematic L

Cadence Virtuoso Layout L

Cadence Virtuoso XL

PDK familiarity

CAD tools (Calibre, Solido)

P-Cell development

Job description

The role requires 7+ years in RF/Analog/Mixed-Signal layout, proficiency with Cadence Virtuoso and PDKs across multiple foundries, and strong skills in layout planning, routing, and

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