Senior Research Scientist, Superconducting Digital Electronics, Quantum AI

Google; Goleta (CA); On-site; USD 174,000 - 252,000; Full time

Benefits offered by this job

Health insurance

401(k) with company match

20 days vacation per year

Sick time and maternity leave

Employee holidays

Job summary

Google is seeking a Senior Research Scientist focused on superconducting digital electronics for Quantum AI in Goleta, CA. This role involves designing circuits for qubit control and collaborating with various teams to develop robust IC designs.

Candidates should possess a master's degree and experience with superconductor logic. The position offers competitive compensation of $174,000–$252,000, along with significant benefits including health insurance and retirement plans.

Qualifications

• Master's degree or equivalent experience in relevant fields.
• Experience performing tape-out of superconducting IC chips.
• One or more published research papers or presentations.

Responsibilities

• Design and simulate superconductor digital logic circuits.
• Develop superconductor digital systems for qubit control.
• Collaborate to validate fully integrated quantum processors.

Skills

Experience in superconductor logic families (e.g., RSFQ, ERSFQ, RQL, HFQ, AQFP)

Proficiency with computer-aided design tools

Leadership in R&D groups

Education

Master's degree in Electrical Engineering or related discipline

PhD in physics or electrical engineering (preferred)

Tools

IC design tools

Electromagnetic simulation tools

Job description

Senior Research Scientist, Superconducting Digital Electronics, Quantum AI

Location: Goleta, CA, USA; Cambridge, MA, USA; Mountain View, CA, USA; Seattle, WA, USA; San Francisco, CA, USA (preferred).

Compensation: US base salary range $174,000–$252,000 plus bonus, equity, and benefits. Salary determined by role, level, location, and experience.

About the job

As a Research Scientist, your primary focus will be designing and simulating superconductor digital logic circuits (such as SFQ logic and AQFP logic) for qubit control and readout. You will engage in co‑design loops with qubit designers and superconducting digital circuit designers, utilizing advanced IC design tools, numerical circuit simulation techniques and 3‑D electromagnetic modeling to optimize signal integrity, minimize crosstalk, manage thermal budgets, and meet performance metrics required for coherent control of qubits. You will also interface with fabrication engineers to help define and establish robust IC design standards that are compatible for both the sensitive superconducting qubits and the co‑located cryogenic control electronics. This work is critical to building a fully integrated, modular chip stack that combines superconducting qubits with their control electronics directly within the cryogenic environment, accelerating the path toward large‑scale, error‑corrected quantum computing.

Responsibilities

• Design and simulate superconductor digital logic circuits for generating waveforms tailored to qubit control and readout.
• Develop superconductor digital logic systems enabling multiplexed qubit control and readout.
• Address integration issues of superconductor digital electronics such as multi‑layer cell design, full‑chip clock synchronization, flux trapping, and signal integrity.
• Collaborate with teams focused on design, fabrication, and measurement to validate fully integrated quantum processors.
• Publish research papers and present at leading scientific conferences to advance and enhance the field.

Minimum qualifications

• Master's degree in Electrical Engineering, Physics, a related engineering discipline, or equivalent practical experience.
• Experience in superconductor logic families (e.g., RSFQ, ERSFQ, RQL, HFQ, AQFP).
• Experience performing tape‑out of a superconducting IC chip.
• One or more published research paper or presentation at a relevant scientific conference.

Preferred qualifications

• PhD in physics, electrical engineering, or a related engineering discipline.
• 7 years of research/industry experience in the design and simulation of superconductor digital logic circuits with 3 years of experience leading an R&D group toward tape‑out and demonstration of superconducting IC chips.
• Experience with full digital design flow including RTL, synthesis, verification, timing closure, place‑and‑route, and post‑fabrication validation.
• Experience with low‑temperature measurements of superconductor digital logic circuits.
• Experience with superconducting qubits.
• Proficiency with computer‑aided design tools and electromagnetic simulation tools.

Benefits

• Health, dental, vision, life, disability insurance
• Retirement benefits: 401(k) with company match
• Paid time off: 20 days of vacation per year, accruing at a rate of 6.15 hours per pay period for the first five years of employment.
• Sick time: 40 hours per year (statutory, where applicable); 5 days per event discretionary.
• Maternity leave (short‑term disability + baby bonding): 28‑30 weeks.
• Baby bonding leave: 18 weeks.
• Holidays: 13 paid days per year.

Applicants in the County of Los Angeles: Qualified applications with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act.

Applicants in San Francisco: Qualified applications with arrest or conviction records will be considered for employment in accordance with the San Francisco Fair Chance Ordinance for Employers and the California Fair Chance Act.

In accordance with Washington state law, we are highlighting our comprehensive benefits package, which is available to all eligible U.S.‑based employees.

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