Senior R&D Engineer, Electrical & FPGA Design (opens in new tab) San Diego, CA →

Synchron, Inc.; San Diego (CA); Presencial; USD 140.000 - 180.000; Jornada completa

Descripción de la vacante

Synchron, Inc. in San Diego, CA seeks a Senior R&D Engineer, Electrical & FPGA Design to own HDL for a low-power implantable FPGA and the surrounding electrical architecture.

You will define supervisory logic, risk controls, and interfaces with external silicon partners, with verification in FPGA emulation before hardware. The role requires hands-on RTL review, safety-focused design, and collaboration with firmware, silicon, and mechanical teams to deliver a safe, compact, and reliable implant

Formación

• Bachelor's degree in electrical engineering, computer engineering, or a related discipline.
• 8+ years in mixed-signal hardware design for miniaturized, high-reliability electronics.
• 5+ years of hands-on FPGA development: VHDL or SystemVerilog, timing closure, and SV-based verification.
• Experience with safety-relevant or fault-tolerant digital systems and ISO 14971 awareness.

Responsabilidades

• Architect and develop synthesizable HDL for a low-power implant FPGA (VHDL/SystemVerilog).
• Own timing closure, clock-domain crossing and low-power clocking.
• Define and verify FPGA/MCU interface and bring-up strategies.
• Develop bench models and emulation for the implant-side serial link.
• Define and implement the implant serial link, framing, error detection, and synchronization.
• Lead design of safety-related controls: redundant monitors, fault detection, and safe-default behavior.
• Design and verify electrical architecture, power, RF, and implantable PCB/flex integration.
• Lead design verification plans, bench/EMC testing, and reliability analyses.
• Collaborate across firmware, silicon, mechanical, and systems engineering to optimize the implant.

Conocimientos

FPGA development

VHDL

SystemVerilog

clock-domain crossing

timing closure

safety-relevant design

RF/inductive power transfer

PCB/flex design

RTL/simulation review

Educación

Bachelor's degree in electrical engineering or computer engineering

Herramientas

Altium Designer

SPICE-class simulation

HFSS/CST/EM tools

Descripción del empleo

If you are unable to complete this application due to a disability, contact this employer to ask for an accommodation or an alternative application process.

Senior R&D Engineer, Electrical & FPGA Design

R&D Admin - TV Full Time San Diego, CA, US

Salary Range: $140,000.00 To $180,000.00 Annually

TITLE

Sr. R&D Engineer, Electrical & FPGA Design

DATE

October 2026

WORK LOCATION

BASE SALARY RANGE

$140,000 - $180,000/year

About the Role

We are seeking a Senior R&D Electrical Engineer to own the electrical and programmable-logic design of Synchron's next-generation implantable electronics, from concept through design verification. The core of the role is defining and developing the HDL for the implant's low-power FPGA: supervisory logic for device health, status, and control, and the implant side of a high-speed serial link to distributed sensing electronics, defined from interface specifications with external silicon partners and proven in FPGA emulation ahead of hardware. The role also owns the surrounding electrical architecture - custom silicon integration, inductive charging and RF telemetry, and PCB/flex design - and carries a safety mandate: detectable faults, redundant monitoring, and defined safe states within a medical device design-controls framework.

Firmware is owned by a dedicated engineer; this role reviews, debugs, or contributes to firmware and test software as the program needs. This is a hands-on, technically deep role: equally comfortable reviewing RTL and schematics as defining system-level architecture.

Key Responsibilities

FPGA / HDL Design

• Architect and develop synthesizable HDL (VHDL or SystemVerilog) for a low-power FPGA serving as the implant's health, status, control, and communications controller; select the FPGA family and configuration approach against power, size, I/O, and configuration-integrity constraints
• Implement supervisory functions: power sequencing, voltage/current/temperature monitoring, watchdogs, fault detection and latching, status reporting to the host MCU, and transition to defined safe states
• Own timing closure, clock-domain crossing, and low-power clocking; develop self-checking testbenches and simulation regressions appropriate to safety-relevant logic
• Define and verify the FPGA/MCU interface (SPI, register map); own FPGA bring-up, diagnostics, and configuration/update strategy

High-Speed Sensor Communications Link

• Define and implement the implant side of the serial link to distributed sensing electronics: clock generation and distribution, line driver/receiver scheme (including emulated-LVDS I/O), framing, synchronization, error detection, and recovery
• Derive and maintain link and timing budgets (jitter, skew, channel loss) and reconcile them with partner models
• Build bench models and FPGA emulation of the link, integrating partner-supplied RTL, to retire risk before final hardware

Safety & Redundant Systems

• Design control and monitoring logic so single faults are detected and contained: redundant or diverse monitors, FPGA/MCU cross-checks, independent shutdown paths, and fail-safe defaults on loss of clock, power, or communication
• Define safe-state behavior and entry/exit conditions; perform FMEA / fault-tree analysis and trace risk controls to design inputs and verification per ISO 14971
• Apply configuration-integrity and single-event-upset mitigations (CRC, readback, redundancy) for chronically implanted programmable logic

Electrical Architecture, Power & RF

• Own the implant's electrical architecture and lead schematic design, component selection, and simulation for ultra-low-power implantable electronics
• Design and characterize the inductive charging link: receive coil geometry and placement, resonant tuning, rectification and regulation, alignment and load tolerance, and tissue heating limits
• Optimize the wireless telemetry link (custom RF, BLE, or inductive) under tissue constraints, including antenna selection, matching, and integration within the hermetic enclosure and header
• Establish power budgets and duty-cycling strategies that balance data throughput against implant longevity
• Lead design of miniaturized, high-density PCB and flex-rigid assemblies in Altium Designer, including layout review, signal integrity, and DFM at implant scale
• Define and execute electrical and FPGA verification plans; lead bench, environmental, and EMC/EMI testing; own failure analysis and design-for-reliability practices
• Serve as electrical and programmable-logic lead within design controls (IEC 60601-1, IEC 62304, ISO 14708); author design inputs, risk analyses, and V&V protocols with traceability from requirements to RTL and test; support regulatory submissions
• Partner with firmware, silicon, mechanical, and systems engineers to co-optimize the implant; review firmware and test-software changes touching the electrical and FPGA interfaces and step in on cross-domain debug
• Work with contract manufacturers and test houses to transfer designs into production

Required Qualifications

• Bachelor's degree in electrical engineering, computer engineering, or a related discipline
• 8+ years in mixed-signal hardware design for miniaturized, high-reliability electronic systems
• 5+ years of hands-on FPGA development: synthesizable VHDL or SystemVerilog, clock-domain crossing and timing closure, and simulation-based verification, on low-power FPGA families
• Working knowledge of serial interface design: source-synchronous or CDR schemes, LVDS/CML signaling, framing and error detection, SPI/I2C, and register-map design
• Demonstrated design of safety-relevant or fault-tolerant digital systems: watchdogs, redundant monitors, fail-safe defaults, fault detection and isolation
• Hands-on experience with inductive power transfer or near-field wireless charging, or equivalent resonant/magnetics design
• Strong high-density PCB and flex-circuit design experience with proficiency in Altium Designer; SPICE-class simulation and signal-integrity analysis
• Ability to read, debug, and review embedded C firmware and test software, and contribute when needed
• Experience bringing electronic subsystems from prototype through design verification into production

Preferred Qualifications

• Custom silicon integration or co-design, including specification development, emulation of partner RTL on FPGA, and bring-up
• Functional-safety or high-integrity design standards (IEC 60601-1 PEMS, IEC 62304, IEC 61508 / ISO 26262 concepts, DO-254-style assurance)
• Antenna or RF front-end design for implantable or body-worn devices, including EM simulation (HFSS, CST, or COMSOL)
• Coil design and EM/thermal modeling for inductive links, including MRI-compatibility constraints on magnetic materials
• Low-noise neural or bioelectric front-end design; embedded firmware development on wireless SoCs with an RTOS and BLE
• Familiarity with ISO 14708, IEC 60601, and FDA guidance for implantable electronics; experience supporting IDE, PMA, or 510(k) submissions