Senior Principal Engineer- SoC/Chip Lead

Renesas Electronics; San Jose (CA); On-site; USD 230,000 - 300,000; Full time

Benefits offered by this job

Bonus opportunities

Job summary

Renesas Electronics is seeking a Senior Principal Engineer- SoC/Chip Lead to drive end-to-end SoC programs from architecture to silicon. You will lead cross-functional teams across digital design, verification, physical design, DFT, firmware, validation, packaging, and product engineering.

The role requires 20+ years in semiconductors with leadership experience and proven success on large-scale ASIC/SoC projects, ideally at 3nm or 5nm nodes.

Qualifications

• 20+ years of semiconductor industry experience with substantial leadership responsibility.
• Proven experience as a Chip Lead, SoC Lead, or equivalent for large-scale ASIC/SoC products.
• Demonstrated success leading advanced-node SoCs, preferably 3nm and/or 5nm.

Responsibilities

• Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.
• Drive SoC planning, integration strategy, execution schedules, risk management, and tape-out readiness.
• Lead cross-functional teams across digital design, verification, physical design, DFT, firmware, validation, packaging, and product engineering.
• Define chip-level architecture, integration requirements, performance targets, and power/area objectives.
• Drive technical decision-making and trade-offs across architecture, implementation, and product requirements.
• Oversee subsystem and IP integration, ensuring successful deployment of complex multi-domain SoCs.
• Partner with analog and SerDes teams to integrate high-speed interfaces and mixed-signal subsystems into the overall chip architecture.
• Lead design reviews, execution reviews, silicon readiness assessments, and post-silicon debug activities.
• Drive issue resolution across the development lifecycle and ensure successful first-pass silicon execution.
• Mentor senior engineers and provide technical leadership across multiple engineering organizations.

Skills

End-to-end technical leadership

RTL Design

Design Verification

Physical Design

DFT

Static Timing Analysis

Low-Power Design

Silicon Bring-up

Strong communication

Education

Bachelor's, Master's, or Ph.D. in Electrical/Computer Engineering

Tools

NoC architectures

High-speed SerDes interfaces

Analog/mixed-signal IPs

Job description

Senior Principal Engineer- SoC/Chip Lead

• Full-time
• Employment Type: Regular (PERM)
• Remote Work Available: No

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.
Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

• Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.
• Drive SoC planning, integration strategy, execution schedules, risk management, and tape-out readiness.
• Lead cross-functional teams across digital design, verification, physical design, DFT, firmware, validation, packaging, and product engineering.
• Define chip-level architecture, integration requirements, performance targets, and power/area objectives.
• Drive technical decision-making and trade-off analysis across architecture, implementation, and product requirements.
• Oversee subsystem and IP integration, ensuring successful deployment of complex multi-domain SoCs.
• Partner with analog and SerDes teams to integrate high-speed interfaces and mixed-signal subsystems into the overall chip architecture.
• Lead design reviews, execution reviews, silicon readiness assessments, and post-silicon debug activities.
• Drive issue resolution across the development lifecycle and ensure successful first-pass silicon execution.
• Mentor senior engineers and provide technical leadership across multiple engineering organizations.
• Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline.
• 20+ years of semiconductor industry experience with substantial leadership responsibility.
• Proven experience as a Chip Lead, SoC Lead, Technical Program Lead, or equivalent role for large-scale ASIC/SoC products.
• Demonstrated success leading advanced-node SoCs, preferably at 3nm and/or 5nm technology nodes.
• Deep understanding of SoC architecture, integration methodologies, and full-chip development flows.
• Strong experience working across:
  • RTL Design, Design Verification, Physical Design, DFT, Static Timing Analysis, Low-Power Design Methodologies and Silicon Bring-up and Productization.
• Experience managing complex schedules, technical dependencies, and cross-functional execution across global teams.
• Strong communication, stakeholder management, and engineering leadership skills.

Preferred Qualifications:

• Prior experience with:
  • High-performance switching silicon
  • Network-on-Chip (NoC) architectures
  • Data movement and interconnect fabrics
  • High-bandwidth memory-centric systems
  • Complex multi-die or chiplet-based architectures
• Hands-on experience integrating:
  • High-speed SerDes interfaces, Analog front-end (AFE) subsystems, Mixed-signal IPs and Advanced PHY technologies.
• Experience with high-bandwidth and low-latency interconnect technologies.
• Knowledge of packaging technologies and signal integrity considerations for high-speed systems.
• Experience in AI, HPC, networking, connectivity, data-center, or memory infrastructure products.
• Prior exposure to UALink, Ethernet switching, switch fabrics, or similar high-performance interconnect technologies is highly desirable.

The expected annual pay range for this position is $230,000-300,000K. This position is also eligible for bonus opportunities. Please note that final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate.

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read ourDiversity & Inclusion Statement .