Senior Principal Digital Design Engineer – AI Connectivity

Astera Labs; San Jose (CA); On-site; USD 205,000 - 255,000; Full time

Benefits offered by this job

Discretionary bonus

Health benefits

Incentives

Job summary

A leading technology company in San Jose is seeking a Senior Principal Digital Design Engineer to lead the architecture of next-generation digital designs for AI infrastructure connectivity. Applicants should have over 12 years of experience in complex SoC product development and deep knowledge of high-speed protocols. This role offers competitive compensation, with a salary range of $205,000 to $255,000, and may include bonuses and benefits. The company values diversity and encourages all qualified individuals to apply.

Qualifications

• B.S. in Electrical Engineering or equivalent required.
• 12+ years of hands-on experience in developing complex SoC products.
• Expertise in micro-architecture development and RTL coding.

Responsibilities

• Define and drive micro-architecture for complex digital blocks.
• Lead RTL implementation of designs from architecture to silicon bring-up.
• Mentor and develop junior engineers to enhance team capabilities.

Skills

Micro-architecture development

Design execution

Cross-functional collaboration

Mentorship

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering or related field

Tools

Cadence

Synopsys

Job description

A leading technology company in San Jose is seeking a Senior Principal Digital Design Engineer to lead the architecture of next-generation digital designs for AI infrastructure connectivity. Applicants should have over 12 years of experience in complex SoC product development and deep knowledge of high-speed protocols. This role offers competitive compensation, with a salary range of $205,000 to $255,000, and may include bonuses and benefits. The company values diversity and encourages all qualified individuals to apply.