Senior PPA Fusion Engineer — ML-Driven IC Design (Equity)

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 168,000 - 264,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Gruppe in Santa Clara, California is looking for a Senior Physical Design Methodology Engineer to join their Networking Silicon team. In this role, you'll develop innovative physical design methodologies improving PPA for cutting-edge communication devices.

With over 10 years' experience in Physical Design Engineering and a strong background in Machine Learning solutions, you'll craft groundbreaking chips in a technology-driven environment.

The base salary is between $168,000 and $264,500 for Level 4 positions, and $196,000 to $310,500 for Level 5.

Qualifications

• 10+ years’ experience in Physical Design Engineering with ML based solution development experience.
• Proven implementation of ML-based solutions.
• Familiar with Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.

Responsibilities

• Develop physical design methodologies for graphics processors and SOCs.
• Innovate solutions to improve PPA.
• Participate in flow and tool development for timing analysis and verification.

Skills

Physical Design Engineering

Machine Learning solutions

Chip design knowledge

Data analysis

Scripting for PPA improvement

Education

MS in Electrical, Computer Engineering, or Computer Science

Tools

PnR tools

Job description

NVIDIA Gruppe in Santa Clara, California is looking for a Senior Physical Design Methodology Engineer to join their Networking Silicon team. In this role, you'll develop innovative physical design methodologies improving PPA for cutting-edge communication devices.

With over 10 years' experience in Physical Design Engineering and a strong background in Machine Learning solutions, you'll craft groundbreaking chips in a technology-driven environment.

The base salary is between $168,000 and $264,500 for Level 4 positions, and $196,000 to $310,500 for Level 5.