Senior Power Delivery Architect

Persimmons Inc.; San Jose (CA); On-site; USD 130,000 - 160,000; Full time

Benefits offered by this job

Competitive salary and benefits package

Flexible PTO

401k

Job summary

Persimmons Inc., based in San Jose, California, seeks a Senior Power Delivery Architect to design power delivery systems for AI accelerators. The role involves architecting from 48V datacenter power down to sub-1V silicon cores, collaborating with silicon and packaging teams for optimal design.

Ideal candidates will have over 8 years of experience in power delivery architecture, a relevant degree, and proficiency in simulation tools. Competitive salary and benefits are offered.

Qualifications

• 8+ years of power delivery experience in chip-level to system-level architecture.
• Expertise in rack-to-silicon PDN design.
• Proficient in power delivery simulation tools.

Responsibilities

• Design the power delivery system for the AI accelerator.
• Develop a roadmap from 48V to sub-1V silicon cores.
• Evaluate high-frequency power delivery technologies.

Skills

Power delivery design

Cross-domain collaboration

Electrical Engineering

Simulation tools (EMIR)

High-density compute systems

Education

Bachelor’s or Master’s in Electrical Engineering

PhD in related technical field (optional)

Tools

Electrothermal simulation tools

Job description

Who we are:

Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, we’re on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn’t imagined yet.

Why join us:

We’re growing fast and looking for bold thinkers, builders, and curious problem‑solvers who want to push the limits of AI hardware and software. If you’re ready to join a world‑class team and play a critical role in making a global impact – we want to talk to you.

What you’ll do:

As a Senior Power Delivery Architect, you will be responsible for designing the complete power delivery system for Persimmons’ AI accelerator — a grid of hundreds of chiplets drawing thousands of amps from a 48V datacenter rack and delivering clean, stable power to silicon cores operating at sub‑1V. This is not a standard board power project. Your primary duties and responsibilities include:

• Architect the rack‑to‑silicon power delivery network, designing the complete roadmap from 48V datacenter busbar power down to sub‑1V silicon cores across a multi‑chiplet grid at hyperscale.
• Own regulator integration strategy — evaluating and deploying high‑frequency, multi‑phase VRMs, Co‑packaged Voltage Regulators (CPVR), and Vertical Power Delivery (VPD) architectures to meet the power density and efficiency demands of our chiplet grid.
• Design the multi‑tier decoupling capacitor hierarchy — bulk, PCB, package, and on‑chip/deep trench — running simulations to maintain stable target impedance across the full delivery stack.
• Model and mitigate extreme di/dt transient events and IR drop across the 400‑chiplet grid, eliminating dynamic voltage droop that would otherwise compromise silicon reliability and performance.
• Partner cross‑functionally with silicon, advanced packaging (2.5D/3D interposers), and thermal teams to run full‑system electro‑thermal and electromagnetic co‑simulations, ensuring power delivery co‑design is baked in from day one.
• You will use AI to attack the highest‑cost parts of power delivery. IR drop analysis, electromigration debugging, power grid optimization, signoff iteration. Wherever the work is repeatable, you will replace manual effort with intelligent agents and structured automation.

What you bring to the table:

• Educational Foundation: Bachelor’s or Master’s degree in Electrical Engineering, Power Electronics, or a related technical field. A PhD with focus on power delivery, electromagnetics, or advanced packaging is a strong plus.
• Proven Experience: 8+ years of hands‑on power delivery experience spanning chip‑level PDN, package‑level power delivery, and system/rack‑level power architecture — ideally on high‑density compute or AI accelerator platforms.
• Specialized Expertise: Deep knowledge of rack‑to‑silicon PDN design including 48V busbar architectures, VRM/CPVR/VPD technologies, multi‑tier decoupling strategy, and transient current management at scale. Experience with 2.5D/3D advanced packaging constraints and their impact on power delivery is highly valued.
• Technical Mastery: Proficiency with power delivery simulation and analysis tools — including EMIR, electrothermal, and electromagnetic co‑simulation — alongside strong fundamentals in power electronics and high‑current system design.
• Collaborative Track Record: Proven ability to drive cross‑domain co‑design across silicon, packaging, thermal, and system teams, owning power delivery architecture from rack to die and delivering production‑ready solutions on schedule.

• Competitive salary and benefits package
• Flexible PTO
• 401k

Please note: Our organization does not accept unsolicited candidate submissions from external recruiters or agencies. Any such submissions, regardless of form (including but not limited to email, direct messaging, or social media), shall be deemed voluntary and shall not create any express or implied obligation on the part of the organization to pay any fees, commissions, or other compensation. Direct contact of employees, officers, or board members regarding employment opportunities is strictly prohibited and will not receive a response.