Senior Physical Design Methodology Engineer, PPA Fusion Compiler

NVIDIA; United States; On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity compensation

Benefits

Job summary

NVIDIA is seeking a Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join our Networking Silicon team. You will develop efficient physical design methodologies for GPUs and SoCs, applying ML-based solutions to improve PPA and tooling across multiple projects.

You will contribute to floorplanning, clock/power distribution, and back-end verification, with data-driven analysis and scripting to optimize performance, area, and power. Competitive base salary with equity and benefits.

Qualifications

• MS in Electrical, Computer Engineering, or Computer Science (or equivalent).
• 10+ years of Physical Design Engineering experience with ML-based solution development.
• Proven implementation of ML-based solutions.
• Familiar with chip design aspects: floorplanning, Clock/Power, Place/Route, integration and verification.

Responsibilities

• Develop efficient physical design methodologies for graphics processors and SoCs.
• Create unique solutions to state-of-the-art physical design problems to improve PPA.
• Leverage ML-based approaches for design convergence and optimization.
• Contribute to flow/tool methodologies for P&R, timing, convergence, EM/IR, thermal management.

Skills

Scripting

Timing analysis

Education

MS in Electrical Engineering / Computer Engineering / CS

Tools

P&R tools

EM/IR analysis tools

Floorplanning tools

Job description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take part in crafting our groundbreaking and innovative chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

• Developing Efficient physical design methodologies for implementation of graphics processors and SOCs.
• Key responsibility includes developing unique and creative solutions to the state-of-the-art physical design problems to improve PPA
• Knowledge and experience to formulate and develop with ML-based solutions
• Participate in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and noise analysis and back-end verification across multiple projects along with chip floorplan, power and clock distribution, chip assembly.
• Data based analysis and algorithmic solutions for PPA check and improvement.

What we need to see:

• MS in Electrical, Computer Engineering, computer science (or equivalent experience)
• 10+ years' experience in Physical Design Engineering with ML based solution development experience
• Proven implementation of ML-based solutions
• Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.
• Staring knowledge of Physical design with convergence in timing/EM/IR with best PPA
• Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
• Familiar with various process related design issues including Design for Yield and Manufacturability, EM and IR closure and thermal management.
• Solid understanding of standard industry PnR tools and analysis tools, Capable of extensive scripting to check and improve PPA

NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 5, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.