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A technology company is seeking a Senior Physical Design Engineer – Place & Route (PnR) to drive block and chip-level design. This remote position requires expertise in Cadence Innovus and extensive experience in PnR for large-scale SoCs. The role includes managing floorplanning, power grid design, and balancing PPA trade-offs. The expected salary is $140,000 to $160,000 annually, with comprehensive benefits.
Position: Senior Physical Design Engineer – Place & Route (PnR) - Remote
Location: Remote (within the U.S.)
Employment Type: Full-time (Salary + Benefits + Bonus) or Contractor
Eligibility: U.S. Citizens or Green Card holders.
Description:
Owns and drives block- and chip-level physical design in Cadence Innovus for GF 22nm. Leads floorplanning, power grid design, placement, CTS, routing, and congestion management. Provides guidance on design partitioning, hierarchy planning, and physical verification (DRC/LVS). Plays a key role in balancing power, performance, and area (PPA) trade-offs and delivering design closure on schedule.
The anticipated annual base salary for this position is between $140,000 to $160,000, which also includes a comprehensive benefits package.
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