Senior Physical Design Engineer

California Jobs; Hayward (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A cutting-edge AI/ML hardware startup is seeking a Senior Physical Design Engineer to lead the physical implementation of complex chip designs. You will work across the full lifecycle of chip development, collaborating with architects and partners to ensure high-performance outcomes. This role offers an opportunity to contribute to groundbreaking technology in a dynamic environment.

Qualifications

• Minimum BSEE/CE + 11 years or MSEE/CE + 6 years experience.
• Proven experience in physical implementation of high-performance network fabrics.

Responsibilities

• Build and support the CAD tool flow for physical implementation.
• Define and construct major physical structures including power delivery networks.
• Execute on block-level and top-level physical implementation.

Skills

SystemVerilog

Python

Perl

Education

BSEE

MSEE

Tools

Cadence Genus

Innovus

Synopsys ICC2

FusionCompiler

Tempus

PrimeTime SI

PrimeTime PX

StarRC

ICV

Calibre

Job description

This Series B AI/ML hardware startup who recently received $125M in funding from Nvidia is developing groundbreaking hardware, software, and systems to solve the critical bottlenecks in next-generation computing workloads – at any scale – across hyperscale cloud, edge, enterprise, 5G/6G, and automotive infrastructure.

They are looking for a Senior Physical Design Engineer to join their team! In this role, you contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout.

Location: Mountain View, CA / Raleigh, NC / Boston, MA

Job Responsibilities

• Build and support the CAD tool flow for physical implementation in a cloud-first development environment.
• Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders.
• Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies.
• Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout.
• Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff

Job Requirements

• Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes.
• Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre.
• Strong familiarity with various analysis tools such as Redhawk, Voltus.
• Experience with circuit analysis using HSPICE is a plus.
• Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages.
• Minimum BSEE/CE + 11 years or MSEE/CE + 6 years experience.

All candidates must be authorized to work in the United States