Senior Mixed-Signal Verification Engineer -Power Management ICs

TylSemi; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

TylSemi is seeking a Senior Mixed-Signal Verification Engineer to lead verification of power management ICs. You will develop plans, create analog behavioral models, and perform analog-digital co-simulation across industry-standard tools, ensuring robust mitigation of non-idealities and corner-case performance.

The role requires deep expertise in mixed-signal verification, RNM modeling, and system-level thinking with strong collaboration across analog, digital, and system teams.

Qualifications

• 5+ years hands-on experience in mixed-signal verification of PMICs or analog/mixed-signal SoCs.
• RNM and Verilog-A behavioral modeling proficiency.
• Strong understanding of power converter topologies (buck, multi-phase, 3-level buck, switched-capacitor).
• Experience with MATLAB/Simulink for system-level modeling and testbench reference generation.

Responsibilities

• Develop and execute mixed-signal verification plans for high-current IVR designs.
• Build and maintain analog behavioral models (Verilog-A / SystemVerilog real-number modeling).
• Perform analog-digital co-simulation using Cadence/Synopsys tools.
• Create testbenches for key metrics: transient response, loop stability, efficiency, ripple, over-current/over-voltage, startup/shutdown.
• Run regressions across PVT corners, Monte-Carlo, and corner-case scenarios.
• Debug mixed-signal issues at transistor and behavioral levels.
• Collaborate with analog/digital designers and system engineers to close verification coverage.
• Develop automated verification scripts and improve methodology for faster turnaround.
• Support post-silicon validation by correlating with lab measurements.

Skills

Mixed-signal verification

Verilog-A RNM modeling

SystemVerilog & UVM

Analog-digital co-simulation

Testbench development

Power electronics knowledge

MATLAB/Simulink

Education

BSEE / MSEE

Tools

Cadence Xcelium

Spectre

Synopsys VCS

AMS Designer

Cadence Virtuoso

Job description

Senior Mixed-Signal Verification Engineer - Power Management ICs

What You’ll Do

• Develop and execute mixed-signal verification plans for high-current IVR designs.
• Build and maintain analog behavioral models (Verilog-A / SystemVerilog real-number modeling) for power stages, integrated inductors, PDN, and analog blocks.
• Perform analog-digital co-simulation using industry-standard tools (Cadence Xcelium + Spectre, Synopsys VCS + FineSim/CustomSim, or AMS Designer).
• Create testbenches for key performance metrics: transient response (load steps), loop stability, efficiency, ripple, over-current / over-voltage protection, and startup/shutdown sequences.
• Run regressions across PVT corners, Monte-Carlo analysis, and corner-case scenarios.
• Debug mixed-signal issues at both transistor-level and behavioral-level.
• Collaborate closely with analog designers, digital designers, and system engineers to close verification coverage.
• Develop automated verification scripts and improve verification methodology for faster turnaround.
• Support post-silicon validation by correlating simulation results with lab measurements.

What We’re Looking For

• 5+ years of hands-on experience in mixed-signal verification of power management ICs or analog/mixed-signal SoCs.
• Strong proficiency in mixed-signal simulation flows :
• Real Number Modeling (RNM) and Verilog-A behavioral modeling
• Solid understanding of power converter topologies (buck, multi-phase, 3-level buck, switched-capacitor converters).
• Good knowledge of digital control concepts for power converters (PID controllers, DPWM, digital feedback loops).
• Experience with MATLAB/Simulink for system-level modeling and testbench reference generation.
• Proficiency in SystemVerilog and UVM for digital/mixed-signal testbenches.
• Familiarity with Cadence Virtuoso, Spectre, or Synopsys CustomSim for analog simulation.
• Understanding of analog non-idealities (quantization effects, loop delay, sensor offsets, PDN resonances, inductor non-linearities).
• BSEE / MSEE with 8+ years relevant experience.

Nice to Have

• Experience verifying high-frequency IVRs, PoL regulators, or high-current power delivery systems.
• Experience with SIMPLIS, PLECS, or Simulink for system-level power electronics validation.
• Familiarity with digital PID controller verification and fixed-point arithmetic effects.
• Exposure to advanced packaging and on-die inductor modeling.
• Scripting skills in Python, Perl, or Tcl for automation.

About TylSemi, Inc.

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That’s what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.

• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location

• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We’re not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else’s roadmap. You're here to define it.

• Bias for action. We move fast. Analysis paralysis doesn't fly here.

• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.

• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.

• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.

• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.