Principal Mixed Signal RTL Design Engineer

TYLsemi; San Jose (CA); Hybrid; USD 223,125 - 301,875; Full time

Job summary

TylSemi, Inc. is seeking a lead for micro-architecture and RTL design of a mixed-signal chiplet focused on intelligent power optimization for AI/HPC.

Responsibilities include translating MATLAB/Simulink controller models to production RTL, implementing digital PID/cascade loops, and collaborating with analog designers to optimize loop performance across PVT corners while aiding silicon bring-up.

Qualifications

• Strong mixed-signal background with power circuits and digital control systems.
• Proven ability to convert control algorithms into clean, synthesizable RTL (HDL Coder or hand-coded).
• Deep knowledge of digital PID implementation: quantization, sampling, delay, fixed-point, limit cycling.

Responsibilities

• Micro-architect and own toplevel RTL for mixed-signal chip with analog circuits and digital logic.
• Architect/d implement digital PID/cascade control loops for high-frequency IVRs.
• Translate validated models into production-quality RTL (Verilog/SystemVerilog).
• Design/implement supporting digital blocks: ADC interface, DPWM.
• Collaborate with analog designers on loop compensation and sensor design.
• Analyze and optimize area, power, timing, and metastability across PVT corners.
• Support silicon bring-up, debugging, and lab hardware.

Skills

Mixed-signal background

HDL Verilog/SystemVerilog

Digital PID implementation

Digital control systems

DPWM / digital PWM modulators

Analog-digital co-simulation

Silicon bring-up / debugging

HDL Coder experience

Education

BSEE / MSEE or PhD

Tools

Synopsys VCS

Verdi

Design Compiler

PrimeTime

Cadence flows

Job description

About The Role

• Lead the micro-architecture and RTL design for Mixed-Signal chiplet focused on intelligent power optimization solutions for AI and high-performance computing.

What You\'ll Do

• Micro-architect and own toplevel RTL for Mixed-signal chip with analog circuits, micro-controller and other logic functions
• Architect, and implement digital PID / cascade control loops (voltage-mode, current-mode, or hybrid) for high-frequency multi-phase IVRs.
• Develop micro-architecture and implement RTL for control of mixed-signal circuits
• Translate validated MATLAB/Simulink controller models into production-quality RTL (Verilog / SystemVerilog) using HDL Coder or manual high-quality coding.
• Design and implement supporting digital blocks: ADC interface, DPWM (digital PWM)
• Collaborate closely with analog designers on loop compensation, sensor design, quantization effects, and delay budgeting.
• Analyze and optimize for area, power, timing, and metastability in the digital controller across PVT corners.
• Support silicon bring-up, debug, and controller on lab hardware.

What We’re Looking For

• Strong mixed-signal background: Solid understanding of power circuits and digital control systems, digital filters etc.
• Proven experience converting control algorithms into clean, synthesizable RTL (HDL Coder or hand-coded Verilog/SystemVerilog).
• Deep knowledge of digital PID implementation challenges: quantization, sampling effects, computational delay, fixed-point arithmetic, and limit cycling.
• Familiarity with high-frequency power converter control and digital PWM modulators (DPWM).
• Experience with mixed-signal verification flows (analog-digital co-simulation).
• Good understanding of analog effects impacting digital control: loop delay, sensor non-idealities, inductor non-linearities, PDN resonances.
• Proficiency in digital design tools: Synopsys VCS, Verdi, Design Compiler, PrimeTime (or equivalent Cadence flow).
• BSEE / MSEE or PhD with 8+ years of relevant experience in power management ICs or high-performance mixed-signal design.

Nice to Have

• Prior experience designing digital controllers for integrated voltage regulators (IVRs), point-of-load (PoL) converters, or high-current AI/HPC power delivery.
• Experience with formal verification or assertion-based mixed-signal verification.

About TylSemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That\'s what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn\'t a nice-to-have. It\'s the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore\'s Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they\'re all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We\'re entering the market at exactly the moment when every major AI/HPC player needs what we\'re building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We\'re not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We\'re building to win.

What We Value

• Ownership mindset. You\'re not here to execute someone else\'s roadmap. You\'re here to define it.
• Bias for action. We move fast. Analysis paralysis doesn\'t fly here.
• Deep technical expertise. This is hard engineering. We need people who\'ve shipped real silicon and debugged real hardware.
• Low ego, high standards. We don\'t care about titles or politics. We care about results.

The Ask

If you\'re reading this, you\'re probably comfortable. You have a good job at a stable company with all the benefits.

We\'re asking you to walk away from that and bet on us.

Here\'s Why You Should

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we\'re building.
• The team has done this before. We\'ve built and exited semiconductor companies at scale. This isn\'t our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You\'re not optimizing someone\'s ad click-through rate. You\'re building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you\'re the kind of person who wants to take the shot, we\'d love to talk.

READY TO JOIN?

The Pay Range For This Role Is

175,000 - 350,000 USD per year (San Jose (HQ))