Senior Memory System Engineer

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 184,000 - 287,500; Full time

Job summary

NVIDIA Gruppe is seeking a Senior Memory System Engineer to join their ASIC Memory Subsystem team. You will work closely with various teams to design cutting-edge memory technology for NVIDIA CPUs and SoCs.

The ideal candidate should have at least 10 years of experience in memory subsystem design, a strong education background in Electrical or Computer Engineering, and experience in both Python and C/C++ for development and analysis. Competitive salary and benefits are offered.

Qualifications

• 10 years of proven experience in DRAM design, module design, or memory subsystem design.
• Deep understanding of memory design, features, ECC algorithms, and SI/PI in DDR, LPDDR, and HBM.
• Experience in design, bring-up, and validation for memory failure analysis.
• Strong understanding of memory subsystem interaction with cache, memory controller, and PHY.

Responsibilities

• Analyze future DDR/LPDDR/HBM technologies for next‑generation SoCs.
• Collaborate with ASIC architects, designers, and firmware teams.
• Define memory module, package, and PCB layouts for system workloads.
• Debug and validate memory evaluation and investigate failure issues.
• Collaborate with DRAM suppliers to develop memory technology.

Skills

DRAM design

Memory subsystem design

Python

C/C++

Interpersonal skills

Education

Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field

Job description

Senior Memory System Engineer – NVIDIA

NVIDIA is looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team. In this role, you will work with memory controller/PHY, platform/system architects, firmware, SI/PI, and memory suppliers to design and architect cutting‑edge, high‑speed, low‑power memory technology for NVIDIA CPUs and SoCs.

Responsibilities

• Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function, and RAS for next‑generation SoCs and systems.
• Collaborate with ASIC architects, designers, software and firmware teams to drive memory technology and associated requirements for memory controllers.
• Define memory module, package, and PCB layouts appropriate to system workloads.
• Debug and bring up memory evaluation/validation and investigate failure issues on memory technology.
• Collaborate with DRAM suppliers and industry partners to develop memory and related component technology.

Qualifications

• Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience).
• 10 years of proven experience in DRAM design, module design, or memory subsystem design.
• Deep understanding of memory design, features, ECC algorithms, and SI/PI (training algorithm) in DDR, LPDDR, and HBM.
• Strong understanding of memory subsystem interaction with cache, memory controller, and PHY.
• Experience in design, bring‑up, and validation for memory failure analysis.
• Experience with Python and C/C++ for development and memory workload analysis.
• Strong user documentation and interpersonal skills.

Compensation & Benefits

Competitive base salary ranging from $184,000 to $287,500 USD for Level4 and $224,000 to $356,500 USD for Level5, plus equity and a generous benefits package.

EEO Statement

NVIDIA is committed to fostering a diverse work environment and is proud to be an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.