Senior Manager, High-Speed Analog & PHY Design

Advanced Micro Devices; Boxborough (MA); Hybrid; USD 150,000 - 190,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD is seeking a Memory I/O design team leader in Boxborough, MA to drive the definition, specification, and implementation of future LPDDR IPs. You will guide circuit architecture for high-speed analog/digital blocks, calibrations and models for link performance, and work across Analog, Digital, Firmware, and Verification teams to ensure robust PHY solutions.

The role requires strong analytical thinking, risk awareness, and a proactive, collaborative mindset.

Qualifications

• Lead multiple PHY designs with silicon results.
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Responsibilities

• Define circuit architecture and implement low power, area-efficient LPDDR PHY blocks
• Collaborate with Analog Mixed Signal, Digital Design and Firmware teams for PHY architecture
• Oversee execution and deliverables across customers and stakeholders
• Develop models for link-level performance simulations and apply to design optimization
• Document micro-architecture and algorithms; guide cross-functional teams
• Contribute to development flows to improve efficiency and quality

Skills

Team management

PHY design

High speed IOs

Circuit modeling

RTL/FW familiarity

Education

Bachelor's/Master/PhD in EE/CE

Tools

MATLAB/Simulink

Verilog/AMS

EDA tools

Job description

AMD is seeking a Memory I/O design team leader in Boxborough, MA to drive the definition, specification, and implementation of future LPDDR IPs. You will guide circuit architecture for high-speed analog/digital blocks, calibrations and models for link performance, and work across Analog, Digital, Firmware, and Verification teams to ensure robust PHY solutions.

The role requires strong analytical thinking, risk awareness, and a proactive, collaborative mindset.