Senior Interconnect Quality Engineer - High-Speed Hardware

OpenAI; Los Angeles (CA); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Competitive salary

Health insurance

Flexible working hours

Job summary

A leading artificial intelligence company in California is seeking a Component and Product Quality Engineer to lead quality initiatives for advanced interconnect components. This role involves defining and tracking quality metrics, driving quality-by-design, and collaborating with various teams to ensure high standards are met throughout the product lifecycle. Candidates should have over 7 years of experience in quality engineering related to high-speed hardware, strong problem-solving skills, and the ability to manage supplier performance. This position is critical for optimizing AI-native silicon solutions.

Qualifications

• 7+ years of experience in quality engineering or manufacturing quality.
• Hands-on experience with high-speed copper interconnect products.
• Strong command of problem-solving and quality tools.

Responsibilities

• Own quality for advanced interconnect components and assemblies.
• Drive quality-by-design through design reviews and plant selections.
• Define and track quality and reliability metrics.

Skills

Quality engineering

Problem-solving

High-speed interconnects

Supplier management

Technical communication

Education

Bachelor's degree in relevant field

Tools

Quality management tools (8D, 5-Whys)

Job description

A leading artificial intelligence company in California is seeking a Component and Product Quality Engineer to lead quality initiatives for advanced interconnect components. This role involves defining and tracking quality metrics, driving quality-by-design, and collaborating with various teams to ensure high standards are met throughout the product lifecycle. Candidates should have over 7 years of experience in quality engineering related to high-speed hardware, strong problem-solving skills, and the ability to manage supplier performance. This position is critical for optimizing AI-native silicon solutions.