Senior Hardware Security ASIC Engineer

MaC VC; San Diego (CA); On-site; USD 146,000 - 218,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego seeks an experienced Hardware Design Engineer with 6+ years of ASIC design to join the Hardware Security team.

The role covers architecture, microarchitecture, RTL design, verification, and silicon testing, with exposure to state-of-the-art security solutions and countermeasures. You will collaborate cross-functionally on a high-profile platform, work through design flow stages from architecture to timing closure, and contribute to secure,

Qualifications

• Bachelor's degree in electrical engineering or related sciences.
• 6+ years of experience in ASIC design, verification, validation, integration, or related work experience.
• Experience and understanding of ASIC design flow: Architecture, Microarchitecture, verilog/system-verilog RTL design, Clock Domain Crossings, DFT, synthesis, and timing closure.
• Knowledge of bus protocols, clocks/resets, debug concepts.
• Problem solving, strong communication and teamwork skills.
• Self-driven, motivated, able to work with minimum supervision.

Responsibilities

• Contribute to architecture, microarchitecture, RTL design, verification, and IP development.
• Lead synthesis, timing closure, and silicon testing.
• Collaborate with cross-functional teams on security features and countermeasures.
• Support validation and bring-up of silicon.

Skills

ASIC design

RTL design

Timing closure

DFT

Synthesis

Clock Domain Crossing

Bus protocols

Debug concepts

Communication

Teamwork

Education

Bachelor's degree in EE or related field

Master's or PhD preferred

Tools

Verilog/SystemVerilog

Synthesis tools

Verification tools

Timing analysis tools

Job description

Qualcomm Technologies, Inc. in San Diego seeks an experienced Hardware Design Engineer with 6+ years of ASIC design to join the Hardware Security team.

The role covers architecture, microarchitecture, RTL design, verification, and silicon testing, with exposure to state-of-the-art security solutions and countermeasures. You will collaborate cross-functionally on a high-profile platform, work through design flow stages from architecture to timing closure, and contribute to secure,