Senior Hardware Design Engineer - High-Density PCB & AI

Google; Sunnyvale (CA); On-site; USD 159,000 - 230,000; Full time

Job summary

Google is seeking a hardware design engineer in Sunnyvale, CA, to lead board-level electrical design for data center hardware and AI infrastructure. You will manage concept through high-volume manufacturing, driving SI/PI, power distribution, and signal integrity within a fast-paced team.

You will collaborate with Silicon/ASIC, Mechanical, Firmware, and Manufacturing teams to deliver integrated PCBAs that meet performance and reliability targets for Google's infrastructure.

Qualifications

• Bachelor’s degree or equivalent in Electrical/Computer Engineering, Physics, or related field.
• 4 years of hardware development and board-level electrical design experience.
• Experience with schematic capture and PCB layout review tools (Cadence Concept, OrCAD, Allegro, Altium).
• Experience in lab bring-up, hardware debugging, and electrical validation using test equipment.

Responsibilities

• Own end-to-end board-level electrical design, including schematic capture and BOM creation.
• Define PCB stackup, layout guidelines, and routing constraints with PCB layout engineers.
• Collaborate with SI/PI engineers to implement high-speed buses and power delivery networks.
• Lead board bring-up, functional validation, and lab electrical characterization.
• Work with cross-functional teams and suppliers to resolve DFM/DFT challenges during NPI builds.

Skills

Hardware design experience

Schematic capture

PCB layout

Lab bring-up

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, or related field

Master's or PhD in Electrical Engineering, Computer Engineering, Physics, or related field

Tools

Cadence Concept

OrCAD

Allegro

Altium

Job description

Google is seeking a hardware design engineer in Sunnyvale, CA, to lead board-level electrical design for data center hardware and AI infrastructure. You will manage concept through high-volume manufacturing, driving SI/PI, power distribution, and signal integrity within a fast-paced team.

You will collaborate with Silicon/ASIC, Mechanical, Firmware, and Manufacturing teams to deliver integrated PCBAs that meet performance and reliability targets for Google's infrastructure.