Senior Hardware Architect: Edge AI Micro-Architect (BayArea)

Quadric; Burlingame (CA); On-site; USD 110,000 - 270,000; Full time

Benefits offered by this job

Competitive salary

Equity

Medical, dental, and vision

401(k)

Unlimited PTO

Office lunches

Caltrain access

Downtown Burlingame location

Collaborative environment

Career development

Job summary

Quadric is seeking a senior chip design engineer to contribute across all stages of the processor design cycle. Located in the California Bay Area, you will regularly collaborate from our Burlingame office and participate in on-site and off-site meetings to align on priorities.

We prefer candidates with a strong background in CPU/GPU/ASIC front-end design and expertise in SystemC/SystemVerilog, Verilog, and low-power techniques.

Qualifications

• BS/MS or Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ASIC front-end design.
• Proficiency in SystemC, SystemVerilog, or Verilog.
• Strong background in computer architecture.
• Knowledge of design techniques for low power digital design.
• Knowledge of VCS & Verilog/C Co-Sim.
• Experience in data-parallel hardware design for high-performance computing.
• FPGA design experience is a plus.
• Experience in logic synthesis and performance modeling.

Responsibilities

• Contribute to the definition of the processor architecture by understanding its applications.
• Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog.
• Own Power, Performance & Area (PPA) optimization.
• Contribute to timing closure through full product cycle (front end, back-end, tapeout).

Skills

SystemC

SystemVerilog

Verilog

CPU/GPU/ASIC front-end design

Computer architecture

Low power digital design

VCS & Verilog/C Co-Sim

Data-parallel hardware design

Education

BS/MS or Ph.D. in Electrical or Computer Engineering

Tools

VCS

Job description

Quadric is seeking a senior chip design engineer to contribute across all stages of the processor design cycle. Located in the California Bay Area, you will regularly collaborate from our Burlingame office and participate in on-site and off-site meetings to align on priorities.

We prefer candidates with a strong background in CPU/GPU/ASIC front-end design and expertise in SystemC/SystemVerilog, Verilog, and low-power techniques.