Senior FPGA Verification Engineer (DO-254)

PeoplePilot; Melbourne (FL); On-site; USD 120,000 - 140,000; Full time

Job summary

PeoplePilot in Melbourne, FL is seeking a Hardware Verification Engineer - DO-254 for an onsite role. The position requires 8 to 20 years of DO-254 and hardware verification experience, with SystemVerilog/UVM and FPGA verification in lab testing or design verification.

The candidate will coordinate with offshore or remote teams and provide DO-254 process documentation guidance to the verification team. Proficiency in VHDL/Verilog/SystemVerilog and timing analyses is essential, along with strong

Qualifications

• Must-have DO-254 experience
• Must-have hardware verification experience
• Experience with SystemVerilog and/or UVM
• FPGA verification in lab testing and/or hardware FPGA design verification testing
• Ability to coordinate with offshore or remote teams
• Ability to provide DO-254 process documentation guidance to the verification team
• Experience developing code and testbenches using VHDL, Verilog, and SystemVerilog
• Experience with static timing, linting, and clock-domain-crossing analysis
• Experience with requirements capture, decomposition, architecture development, synthesis, placement, and routing
• Degree in a STEM field

Skills

DO-254 experience

Hardware verification experience

SystemVerilog/UVM

FPGA verification in lab/testing

Coordinate with offshore/remote teams

DO-254 documentation guidance

VHDL/Verilog/SystemVerilog coding

Static timing, linting, CDC analysis

Requirements capture & architecture

Education

Degree in STEM field

Job description

PeoplePilot in Melbourne, FL is seeking a Hardware Verification Engineer - DO-254 for an onsite role. The position requires 8 to 20 years of DO-254 and hardware verification experience, with SystemVerilog/UVM and FPGA verification in lab testing or design verification.

The candidate will coordinate with offshore or remote teams and provide DO-254 process documentation guidance to the verification team. Proficiency in VHDL/Verilog/SystemVerilog and timing analyses is essential, along with strong