Senior FPGA Routing & Compiler Engineer

Altera; United States; On-site; USD 187,000 - 271,000; Full time

Benefits offered by this job

Incentive opportunities

Core compiler technology work

Job summary

Altera is a leader in FPGA innovation and seeks a Senior FPGA Compiler Engineer (Routing) to advance routing and timing closure within the compiler toolchain. You will design and optimize routing algorithms and collaborate with architecture, synthesis, timing, and hardware teams to improve performance and scalability.

The ideal candidate has 9+ years in FPGA/ASIC design tools, strong graph algorithms, and fluency in C/C++.

Qualifications

• 9+ years of experience in FPGA/ASIC design tools or EDA.
• Strong background in graph algorithms, data structures, and optimization.
• Proficiency in C/C++ and software development best practices.
• Experience with FPGA/ASIC design flows (placement, routing, timing closure).

Responsibilities

• Design, implement, and optimize FPGA routing algorithms to improve performance, routability, and timing closure.
• Contribute to the FPGA compiler flow, including placement, routing, and timing-driven optimization.
• Analyze and improve runtime, memory efficiency, and scalability of routing algorithms for large designs.
• Cross-functional collaboration with architecture, synthesis, timing (STA), and hardware teams.
• Investigate routing congestion, timing violations, and design bottlenecks; develop solutions to improve convergence.
• Toolchain integration: integrate routing features into existing compiler infrastructure and ensure robustness across diverse customer use cases.

Skills

Graph algorithms

Optimization techniques

C/C++

FPGA/ASIC design flows

Education

Bachelor's or Master's in Electrical/Computer Engineering or Computer Science

Tools

Quartus

Vivado

Python

Tcl

Job description

Altera is a leader in FPGA innovation and seeks a Senior FPGA Compiler Engineer (Routing) to advance routing and timing closure within the compiler toolchain. You will design and optimize routing algorithms and collaborate with architecture, synthesis, timing, and hardware teams to improve performance and scalability.

The ideal candidate has 9+ years in FPGA/ASIC design tools, strong graph algorithms, and fluency in C/C++.