Senior FPGA Engineer - Vitis HLS & High-Performance HW

Castelion Corporation; Allen (TX); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Generous benefits package

Job summary

Castelion is seeking a Senior FPGA Engineer to design and optimize FPGA-based processing using Vitis HLS and C/C++ in a fast-moving defense tech environment. You will collaborate with hardware, software, and systems teams to deliver high-performance digital solutions for mission-critical hardware.

The role requires hands-on experience with VHDL/Verilog, FPGA toolchains, and Xilinx platforms, with a strong emphasis on synthesis, timing closure, and hardware validation in a high-stakes setting.

Qualifications

• : Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
• Demonstrated experience using Vitis HLS or similar High-Level Synthesis tools
• Strong C/C++ programming experience for hardware-oriented development
• Experience generating VHDL or Verilog from HLS workflows
• Familiarity with FPGA development flows including simulation, synthesis, and timing closure
• Experience with Xilinx/AMD FPGA platforms and toolchains

Responsibilities

• Develop FPGA-based implementations using Vitis HLS to generate VHDL/Verilog from C/C++ code
• Translate algorithms and system requirements into efficient hardware architectures optimized for performance and latency
• Develop and optimize high-level synthesis pipelines and dataflow architectures
• Collaborate with software, avionics, and systems engineers to integrate FPGA functionality into embedded platforms
• Perform FPGA simulation, synthesis, timing analysis, and hardware validation
• Optimize designs for throughput, determinism, and resource utilization
• Support hardware integration, board bring-up, and debugging as needed
• Contribute to verification and testing of FPGA functionality

Skills

Vitis HLS

C/C++ for hardware

VHDL/Verilog

FPGA development

High-Level Synthesis

Education

Bachelors in Electrical/Computer Engineering

Tools

Vivado

Vitis

Xilinx toolchains

Job description

Castelion is seeking a Senior FPGA Engineer to design and optimize FPGA-based processing using Vitis HLS and C/C++ in a fast-moving defense tech environment. You will collaborate with hardware, software, and systems teams to deliver high-performance digital solutions for mission-critical hardware.

The role requires hands-on experience with VHDL/Verilog, FPGA toolchains, and Xilinx platforms, with a strong emphasis on synthesis, timing closure, and hardware validation in a high-stakes setting.