Senior FPGA Engineer

Randstad USA

North Reading (MA)

On-site

USD 190,000 - 200,000

Full time

5 days ago
Be an early applicant

A complete application in a minute

Tailored resume and cover letter, ready to send.

Get past ATS filters

Benefits offered by this job

Full W-2 benefits
Bonuses
Stock options
Paid relocation

Job summary

Randstad USA in North Reading, MA is seeking an experienced FPGA Engineer to design, implement, and verify high-performance FPGA architectures for next-generation automated test equipment. You will collaborate across hardware, software, and systems teams to solve complex signal integrity and high-speed data challenges.

The role offers a full W-2 benefits package, bonuses, stock options, and paid relocation. Work hours are 8am to 4pm in a permanent, onsite position requiring a Bachelor's degree.

Qualifications

  • Minimum 10 years of FPGA design experience.
  • Bachelor's degree required.
  • Experience with high-density, high-speed FPGA architectures.

Responsibilities

  • RTL Design & Architecture: Write clean, maintainable SystemVerilog/Verilog for high-density, high-speed FPGAs (AMD/Xilinx Vivado, Intel/Altera Quartus).
  • System Integration: Integrate embedded processors (e.g., MicroBlaze, ARM Cortex, PCIe controllers) and high-speed serial transceivers (Multi-Gigabit Transceivers).
  • Timing Closure: Perform complex synthesis, place-and-route, Static Timing Analysis (STA), and achieve timing closure on ultra-high-frequency designs.
  • Verification & Debug: Design verification testbenches in SystemVerilog/UVM and perform lab debugging using logic analyzers, high-speed oscilloscopes, and internal FPGA debug tools (e.g., ILA, SignalTap).
  • Cross-Functional Collaboration: Partner with board-level hardware engineers, firmware developers, and software teams to define hardware/software boundary interfaces and ensure system validation.

Skills

RTL Design & Architecture
SystemVerilog/Verilog
High-speed FPGA design
Timing closure
Verification & Debug
Cross-functional collaboration

Education

Bachelor's degree

Tools

Vivado
Quartus

Job description

Job Summary

Seeking an FPGA Engineer for a high growth test equipment development and manufacturing client in the North Reading, MA area.


The FPGA Engineer would be responsible for you will design, implement, and verify high-performance FPGA architectures that power Teradyne's next-generation Automated Test Equipment. You will collaborate with cross-functional teams spanning hardware, software, and systems engineering to solve complex signal integrity, processing, and high-speed data transmission challenges.


Full W-2 benefits offered! Great compensation package including bonuses and stock options! Paid relocation!


Job Details

Location: North Reading, Massachusetts


Job Type: Permanent


Salary: $190,000 - 200,000 per year


Work Hours: 8am to 4pm


Education: Bachelors


Responsibilities


  • RTL Design & Architecture: Write clean, maintainable SystemVerilog/Verilog for high-density, high-speed FPGAs (AMD/Xilinx Vivado, Intel/Altera Quartus).

  • System Integration: Integrate embedded processors (e.g., MicroBlaze, ARM Cortex, PCIe controllers) and high-speed serial transceivers (Multi-Gigabit Transceivers).

  • Timing Closure: Perform complex synthesis, place-and-route, Static Timing Analysis (STA), and achieve timing closure on ultra-high-frequency designs.

  • Verification & Debug: Design verification testbenches in SystemVerilog/UVM and perform lab debugging using logic analyzers, high-speed oscilloscopes, and internal FPGA debug tools (e.g., ILA, SignalTap).

  • Cross-Functional Collaboration: Partner with board-level hardware engineers, firmware developers, and software teams to define hardware/software boundary interfaces and ensure system validation.


Qualifications


  • Experience level: Experienced

  • Minimum 10 years of experience

  • Education: Bachelors (required)


Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.


This posting is open for thirty (30) days.


It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Jr Electrical Engineer FPGA
Jr Electrical Engineer FPGA

Randstad USA • North Reading (MA)

On-site
USD 115,000 - 125,000
Bonuses
Stock options
Electrical Engineer FPGA
Electrical Engineer FPGA

Randstad USA • North Reading (MA)

On-site
USD 150,000 - 165,000
Full W-2 benefits
Bonuses
Stock options
Senior FPGA Architect (Compute Test, North Reading)
Senior FPGA Architect (Compute Test, North Reading)

Teradyne • North Reading (MA)

On-site
USD 155,000 - 248,000
FPGA Developer (Compute Test, North Reading)
FPGA Developer (Compute Test, North Reading)

Teradyne • Reading (MA)

On-site
USD 123,000 - 197,000
Health and dental benefits
Retirement savings plan
Paid vacation & holidays
+1
Senior FPGA Architect
Senior FPGA Architect

Teradyne • Reading (MA)

On-site
USD 164,800 - 263,600
Health and well-being benefits
Retirement savings plans
Tuition assistance programs
Jr. FPGA Developer (Compute Test, North Reading)
Jr. FPGA Developer (Compute Test, North Reading)

Teradyne • North Reading (MA)

On-site
USD 99,000 - 158,000
Health benefits
Retirement plan
Tuition assistance
+1
Senior FPGA Architect (Compute Test, North Reading)
Senior FPGA Architect (Compute Test, North Reading)

Teradyne • Reading (MA)

On-site
USD 155,000 - 248,000
Health and well-being benefits
Tuition assistance programs
Paid vacation & holidays
Jr. FPGA Developer (Compute Test, North Reading)
Jr. FPGA Developer (Compute Test, North Reading)

Teradyne • Reading (MA)

On-site
USD 99,000 - 158,000
Health benefits
Tuition assistance
Paid vacation
FPGA Developer (Compute Test, North Reading)
FPGA Developer (Compute Test, North Reading)

Teradyne • North Reading (MA)

On-site
USD 123,000 - 197,000
FPGA Design Engineer (MTD, San Jose, CA)
FPGA Design Engineer (MTD, San Jose, CA)

Teradyne • San Jose (CA)

On-site
USD 135,400 - 216,600