Senior FPGA Design Engineer

Ouster, Inc.; San Francisco (CA); On-site; USD 125,000 - 232,000; Full time

Job summary

Ouster, Inc., a leading technology company in San Francisco, is seeking a skilled senior digital hardware FPGA design engineer to innovate and enhance their lidar systems. The role involves hands-on FPGA development and collaborating with embedded software engineers to ensure successful integration of customer features. Candidates should be proficient in HDL, C++, and have significant experience in FPGA technologies and embedded systems. With competitive pay and comprehensive benefits, Ouster prioritizes employee well-being and inclusivity.

Benefits

15 vacation days annually

10 paid holidays

401K match up to 4%

Medical, vision and dental plans with premiums covered at 100%

Life insurance and disability coverage

Complimentary dinner catered nightly

Qualifications

• 5+ years of experience in FPGA development.
• Proficient in Verilog and SystemVerilog.
• Strong experience with scripting languages and automation.

Responsibilities

• Define, develop, integrate, and test features for FPGA systems.
• Work on high impact customer-facing features.
• Perform hands-on work using laboratory tools for testing.

Skills

FPGA development

HDL coding

C++ programming

scripting languages

embedded system development

Education

Bachelors in Electrical, Computer Engineering or equivalent

Masters degree

Tools

Xilinx FPGA toolchain

Intel FPGA toolchain

Vivado

Vitis Tools

Job description

At Ouster, we build sensors and tools for engineers, roboticists, and researchers, so they can make the world safer and more efficient. Weve transformed LIDAR from an analog device with thousands of components to an elegant digital device powered by one chip-scale laser array and one CMOS sensor. The result is a full range of high-resolution LIDAR sensors that deliver superior imaging at a dramatically lower price. Our advanced sensor hardware and vision algorithms are used in autonomous cars, drones and many other applications. If you’re motivated by solving big problems, we’re hiring key roles across the company and need your help!

Ouster Inc. is seeking a senior digital hardware FPGA design engineer to build the next-generation of lidar systems. You will work hands-on with hardware and develop new techniques to improve lidar performance. Your effort includes micro-architecture design, implementation, and testing of the customer facing features in FPGA RTL. The ideal candidate will have experience in all aspects of FPGA design, verification, bring up, and debug, as well as ability in scripting and writing basic low-level drivers to accompany said designs.

Responsibilities :

• Define, develop, integrate, and test features across our FPGA stack
• General FPGA development including RTL, simulation, high-speed digital design, DSP algorithm development, verification, synthesis, and timing analysis.
• Perform hands-on work using laboratory tools for board bring up and troubleshooting.
• Work on high impact customer-facing features and integrate customer feedback in the development process
• Work cross-functionally with embedded software engineers, other ASIC / FPGA designers, and business leaders on functionality, interfaces, and documentation
• Build automation scripts for repetitive tasks to facilitate efficiency and reliability

Qualifications :

• Bachelors in Electrical, Computer Engineering or equivalent. Masters is highly desired.
• 5+ years of experience in FPGA development including HDL code development, simulation, test bench development, synthesis, and timing closure.
• Highly proficient in HDLs like Verilog and SystemVerilog (or VHDL).
• Proficient in C or C++ programming language.
• Experience with Xilinx or Intel FPGA toolchain.
• Strong embedded system development experience in CPU and FPGA based devices such as Xilinx Zynq or Intel Arria devices.

Desirable Qualifications :

• Familiar with HLS, Vivado and Vitis Tools.
• Familiarity with DSP and algorithms development
• Experience with leading verification methodologies like UVM.
• Experience using best practices with version control technologies such as git
• Proficient in some scripting languages such as TCL, Python, bash.
• Experience with industrial safety systems.
• Experience with Functional Safety development processes.

The base pay will be dependent on your skills, work experience, location, and qualifications. This role may also be eligible for equity & benefits. ($125,000-$232,000)

We acknowledge the confidence gap at Ouster. You do not need to meet all of these

requirements to be the ideal candidate for this role.

At Ouster we offer a range of competitive benefits, as we believe in taking care of our employees in all aspects of their lives. Our newly renovated office, located in the Mission District of San Francisco, is a dog-friendly workplace with a kitchen stocked with snacks, fresh fruit and drinks, and a complimentary dinner catered nightly. Additional perks include 15 vacation days / 10 paid holidays annually; paid parental leave; pre-tax commuter or health care / dependent care accounts; 401K match up to 4%; medical, vision and dental plans with premiums covered at 100% for the employee and 75% for dependents (Cigna or Kaiser); life insurance; and short term disability and long term disability. Ouster offers the best benefit options available because we consider the well-being of our employees a top priority.

Ouster is an Equal Employment Opportunity employer that pursues and hires a diverse workforce. Ouster does not make employment decisions on the basis of race, color, religion, ethnic or national origin, nationality, sex, gender, gender-identity, sexual orientation, disability, age, military status, or any other basis protected by local, state, or federal laws. Ouster also strives for a healthy and safe workplace, and prohibits harassment of any kind. Pursuant to the San Francisco Fair Chance Ordinance, Ouster considers qualified applicants with arrest and conviction records for employment. If you have a disability or special need that requires accommodation, please let us know.

Are you open to relocation if you are not local?

Are you aware that this is an onsite in San Francisco, CA role?

Please rate your coding skill in Verilog / SystemVerilog (10 is best)

Please rate your coding skill in C++ (10 is best)

Please rate your coding skill in Python (10 is best)

What programming language are you most proficient in?

Please rate your coding skill in HLS (10 is best)

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Fpga Design Engineer • San Francisco, CA, United States