Senior FPGA Design Engineer

RTX; Fort Wayne (IN); On-site; USD 87,000 - 165,000; Full time

Benefits offered by this job

Medical

Dental

Vision

Life Insurance

Short-term disability

Long-term disability

401(k) match

Flexible schedules

Employee assistance program

Employee Scholar Program

Parental leave

Paid time off

Holidays

Annual short-term incentive

Annual long-term incentive

Job summary

RTX in Fort Wayne, IN seeks a Senior FPGA Design Engineer to lead full‑lifecycle FPGA/ASIC design activities, from architecture through verification. You will define requirements, develop VHDL/Verilog code, perform timing closure, and mentor junior engineers in a multidisciplinary team environment.

The role emphasizes designing for reliability across multiple vendor devices, coordinating with program teams, and delivering well‑documented designs with strong CM practices.

Qualifications

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 5 years of prior relevant experience.
• FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
• Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
• Hands on experience with integration and debug of FPGA/ASIC in a lab environment
• Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
• Experience with source code management, design reviews, and code release in a team development environment.

Responsibilities

• Provide full lifecycle support of production quality FPGA designs for major vendors and device families.
• Generate FPGA designs for gigabit serial interfaces, RF DSP, controls, data links, embedded processing and processor interfaces.
• Translate system level requirements into FPGA requirements.
• Architect FPGA-based systems to determine parts, interfaces and CONOPS.
• Lead FPGA designs and code in VHDL for reliability and maintainability.
• Verify designs with self-checking tests and track coverage.
• Define schedules for FPGA tasking and manage budgets and timelines.
• Create documentation including requirements, verification plan and user guides.
• Lead designs and/or small teams.
• Operate with minimal oversight from management.
• Support internal and external technical reviews.
• Mentor junior engineers.

Skills

FPGA/ASIC design

VHDL/Verilog

Xilinx/Altera/Microchip devices

Vivado/Quartus/Libero

Lab integration/debug

Timing closure

Source control

Education

Bachelor's degree in STEM

Advanced degree in EE or STEM

Tools

Vivado

Quartus Prime Pro

Libero

Job description

Date Posted: 2026-10-26

Country: United States of America

Location: US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A

Position Role Type: Onsite

U.S. Citizen, U.S. Person, or Immigration Status Requirements: The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance

Security Clearance Type: DoD Clearance: Secret

Security Clearance Status: Active and existing security clearance required after day 1

At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world.

The Multi-Product Power & Digital (MPD) department designs FPGAs, circuit cards, and electronics subassemblies for a range of products including missiles/effectors, radars, and electronic warfare systems. The team leverages digital, analog, and power design skills to provide support throughout the product lifecycle from architecture and design through production and sustainment.

The MPD department is seeking a Senior FPGA Design Engineer to join our team. In this role, you will leverage advanced technologies to create cutting‑edge solutions for sensor and effector products. You will partner with experienced, multidisciplinary teams to define requirements, develop architectures, execute detailed design and simulations, and perform integration and verification tasks. You will document your designs within the appropriate configuration management tools and provide comprehensive engineering support throughout the product lifecycle.

This position is an onsite role, located in Fort Wayne, IN.

What You Will Do

• Provide full lifecycle support of production quality FPGA designs for all major vendors and device families including: AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
• Generate FPGA designs for the following applications: gigabit serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing and processor interfaces.
• Support translation of system level requirements into FPGA requirements
• Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)
• Lead FPGA designs and code in VHDL for reliability and maintainability
• Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage
• Define schedules for FPGA tasking and drive execution to the planned budget and schedule.
• Create complete documentation including requirements, verification plan, and user’s guides
• Lead individual designs and/or small teams.
• Operate with minimal oversight from manager.
• Support internal and external technical reviews.
• Engage in knowledge transfer activities and mentorship of junior engineers.

Qualifications You Must Have

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 5 years of prior relevant experience.
  • FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
  • Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
  • Hands on experience with integration and debug of FPGA/ASIC in a lab environment
  • Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
  • Experience with source code management, design reviews, and code release in a team development environment.

Qualifications We Prefer

• One or more advanced degrees in Electrical Engineering or a related Science, Technology, Engineering, or Mathematics (STEM) major. A suitable degree may be counted as 2 years of work experience.
• FPGA/ASIC design experience in one or more of the following areas:
  • Radar processing techniques
  • Image processing techniques for visual and infrared sensors
  • Embedded systems design using ARM, Microblaze, or NIOS processors
  • Gigabit serial interfaces and multi-gigabit transceivers (MGTs)
  • Constrained random verification in UVM using System Verilog
  • Experience with High Level Synthesis (HLS)
  • Experience with vector processors and/or GPUs

• Demonstrated ability to lead teams to achieve schedule, budget and technical commitments.
• Experience with project management tools such as Earned Value and/or Agile Execution.
• Proposal development experience.

What We Offer

Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value: Trust, Respect, Accountability, Collaboration, and Innovation.

This position offers relocation based on candidate eligibility.

This position requires a security clearance. DCSA Consolidated Adjudication Services (DCSA CAS), an agency of the Department of Defense, handles and adjudicates the security clearance process. More information about Security Clearances can be found on the US Department of State government website here: https://www.state.gov/m/ds/clearances/c10978.htm

Indiana: https://careers.rtx.com/global/en/raytheon-indiana-location

#LI-CV1

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified Individuals with a Disability and Protected Veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.

The salary range for this role is 86,800 USD - 165,200 USD. The salary range provided is a good faith estimate representative of all experience levels. RTX considers several factors when extending an offer, including but not limited to, the role, function and associated responsibilities, a candidate’s work experience, location, education/training, and key skills.

• medical
• dental
• vision
• life insurance
• short-term disability
• long-term disability
• 401(k) match
• flexible spending accounts
• flexible work schedules
• employee assistance program
• Employee Scholar Program
• parental leave
• paid time off
• holidays
• annual short-term incentive compensation program
• annual long-term incentive compensation program

Specific benefits are dependent upon the specific business unit as well as whether or not the position is covered by a collective-bargaining agreement.

Payments under these annual programs are not guaranteed and are dependent upon a variety of factors including, but not limited to, individual performance, business unit performance, and/or the company’s performance.

This role is a U.S.-based role. If the successful candidate resides in a U.S. territory, the appropriate pay structure and benefits will apply.

RTX anticipates the application window closing approximately 40 days from the date the notice was posted. However, factors such as candidate flow and business necessity may require RTX to shorten or extend the application window.