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Position: Senior FPGA/ASIC Assurance Engineer
Location: US – MD, Fort Meade (or surrounding area)
Clearance Requirement: Active TS/SCI w/ full scope polygraph
Education Requirement: BS in Electrical Engineering, Computer Science (or related technical field)
Experience Requirement: 14+ Years
The Senior FPGA/ASIC Assurance Engineer is a Subject Matter Expert in FPGA and/or ASIC development to support FPGA/ASIC Assurance efforts in support of DoD. In this role, you will be responsible for reviewing and evaluating various vendor FPGA assurance tools to ensure the tools function as advertised and provide FPGA assurance.
Responsibilities include applying expertise in FPGA/ASIC development and assurance to support DoD projects, reviewing tool capabilities, and assessing the potential benefits and challenges of integrating microelectronic technologies into practical designs and manufacturing processes. You will analyze system requirements, develop high‑level system architectures, and conduct feasibility studies as part of the assurance process.
Contingency: This position is contingent upon the successful completion of security processing and favorable acceptance onto the program by the Customer.
TAP Engineering is an Equal Opportunity Employer and applicants receive lawful consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.
Note: This refined description excludes unrelated postings and boilerplate content found in the original, and preserves the core responsibilities, qualifications, and compliance information relevant to the Senior FPGA/ASIC Assurance Engineer role.