Senior Firmware Engineer

ScaleFlux; Milpitas (CA); On-site; USD 100,000 - 150,000; Full time

Job summary

ScaleFlux is seeking an experienced firmware engineer to develop next-generation CXL Type 3 memory expansion devices. This role includes optimizing firmware and integrating systems with host platforms.

The ideal candidate will have strong skills in embedded systems development, knowledge of high-speed interfaces, and a solid understanding of memory subsystems. Join our Engineering team in Milpitas, California, and contribute to innovative memory technologies.

Qualifications

• Strong experience in embedded systems development at SoC / bare-metal level.
• Hands-on experience with high-speed interfaces such as PCIe Gen5+ and/or CXL.
• Solid understanding of memory subsystems, including DDR initialization and training flows.

Responsibilities

• Develop and optimize firmware for CXL Type 3 devices at SoC / bare-metal level.
• Design and implement features related to memory initialization and runtime management.
• Work on system-level integration with host platforms, including debug and tuning.

Skills

Embedded systems development

High-speed interfaces (PCIe Gen5+/CXL)

Memory subsystems knowledge

Low-level debugging skills

Tools

JTAG

Memory diagnostics tools

Job description

Department: Engineering/Firmware Development

Job Description:

We are looking for an experienced firmware engineer to develop next-generation CXL Type 3 memory expansion devices. The candidate will work across firmware, memory subsystem, and system-level integration.

Key Responsibilities

• Develop and optimize firmware for CXL Type 3 devices at SoC / bare-metal level
• Design and implement features related to memory initialization, training, and runtime management
• Work on system-level integration with host platforms (x86/AMD), including debug and performance tuning
• Collaborate with hardware, validation, and system software teams to bring up new silicon

Required Qualifications

• Strong experience in embedded systems development at SoC / bare-metal level
• Hands‑on experience with high-speed interfaces such as PCIe Gen5+ and/or CXL
• Solid understanding of memory subsystems, including DDR initialization and training flows
• Experience with RAS (Reliability, Availability, Serviceability) features such as ECC, error handling, memory diagnostics, or fault isolation
• Familiarity with industry standards and protocols such as I2C, I3C, SMBus, SPD, ACPI
• Familiarity with low-level debugging tools and methodologies (JTAG, trace, logs, etc.)
• Good understanding of system architecture and hardware/software interactions.

Preferred Qualifications

• Experience with Linux kernel development or driver development (especially memory subsystem or device drivers)
• Knowledge of cache/memory hierarchy, NUMA, or system memory management
• Experience with server platform management technologies such as BMC, IPMI
• Knowledge of OCP standards and management protocols (MCTP, PLDM, SPDM)
• Familiarity with JEDEC standards related to DRAM and memory modules
• Strong problem-solving and debugging skills
• Good written and verbal communication skills
• Self-driven with ability to learn new technologies quickly