Senior Engineer, Physical Design Engineering (ASIC)

Analog Devices; New Jersey; On-site; USD 116,960 - 160,820; Full time

Benefits offered by this job

Medical insurance

Vision insurance

Dental insurance

401k

Paid time off

Discretionary bonus

Job summary

Analog Devices is seeking a Senior Physical Design Engineer to drive the back-end implementation of complex digital/mixed-signal ICs. You will own floorplanning, placement, clock-tree synthesis, routing, and timing closure, coordinating with RTL, verification, DFT, STA, and package teams to ensure successful tapeout.

The role emphasizes strong debugging, constraint development, and flow improvements, with opportunities to mentor junior engineers and contribute to methodology enhancements.

Qualifications

• 5+ years of experience in physical design for ASIC/SoC development.
• Strong background in floorplanning, P&R, CTS, timing closure, and signoff.
• Experience with timing, SI, power optimization, and physical trade-offs.
• Excellent collaboration with RTL, verification, DFT, STA, and package teams.

Responsibilities

• Own physical design implementation for complex digital blocks and subsystems.
• Drive timing closure, congestion analysis, power optimization, and area improvement.
• Perform DRC/LVS/ERC and reliability checks with cross-functional teams.
• Develop constraints and flows to improve quality and efficiency.
• Support tapeout planning and handle interface timing and readiness.

Skills

Physical design

Floorplanning

Place-and-route

Timing closure

Clock tree synthesis

Scripting (TCL, Python)

DRC/LVS/ERC debugging

Collaboration across RTL/STA/DFT

Education

Bachelor’s degree in Electrical/Computer Engineering or related field

Master’s degree in Electrical/Computer Engineering or related field

Tools

Cadence flows

Job description

About Analog DevicesAnalog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X .About the RoleAs a Senior Physical Design Engineer, you will play a key role in the implementation and delivery of complex digital and mixed-signal IC designs. You will work across the physical design flow, from floorplanning through place-and-route, timing closure, physical verification, and tapeout support, helping turn architectural and RTL intent into robust silicon implementation. This role requires strong technical depth in physical design, the ability to solve complex implementation challenges, and effective collaboration with cross-functional teams across the development cycle.Key ResponsibilitiesOwn physical design implementation for complex digital blocks and subsystems, including floorplanning, placement, clock tree synthesis, routing, and physical optimizationDrive timing closure, congestion analysis, power optimization, and area improvement across assigned blocks or subsystemsPerform physical verification activities including DRC, LVS, ERC, and reliability checks in collaboration with relevant teamsDevelop and refine physical design constraints, scripts, and flow improvements to improve quality and execution efficiencyCollaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve design and implementation issuesSupport block-level and top-level integration activities, including interface planning, timing constraint alignment, and implementation readinessAnalyze and debug timing, signal integrity, power, and physical implementation issues across the full backend flowContribute to methodology improvements and help establish best practices for physical design executionParticipate in design reviews and provide clear technical input on implementation trade-offs, risks, and readinessAuthor and maintain documentation for design implementation, constraints, flows, and signoff statusMentor junior engineers on physical design practices, tool usage, and debugging approachesSupport tapeout planning and execution activities to ensure high-quality delivery against project milestonesMust Have SkillsStrong experience in physical design for ASIC/SoC development, including successful implementation through tapeoutExpertise in floorplanning, place-and-route, clock tree synthesis, timing closure, and physical verificationStrong understanding of timing analysis, constraints, signal integrity, power optimization, and physical design trade-offsExperience with industry-standard physical design and signoff tools, including Cadence-based flowsScripting experience in TCL, Python, or similar languages for automation and flow improvementExperience collaborating across cross-functional teams including RTL, STA, DFT, design verification, and package or product engineeringStrong problem-solving and debug skills across backend implementation challengesClear communication and technical documentation skillsDemonstrated ability to independently drive complex blocks or major implementation workstreamsPreferred QualificationsExperience with advanced-node implementation and low-power design methodologiesFamiliarity with mixed-signal integration considerations and top-level implementation challengesExperience improving backend flows, automation, or methodologyPrior mentoring experience or informal technical leadership on project executionPreferred Education and ExperienceBachelor’s degree in Electrical Engineering, Computer Engineering, or related field, or an equivalent combination of education and 5+ years of related experienceMaster’s degree in Electrical Engineering, Computer Engineering, or related field, or an equivalent combination of education and 5+ years of related experienceWe recognize that candidates may not meet every listed requirement. If you bring relevant experience and a willingness to learn, we encourage you to apply.#LI-PG1For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.EEO is the Law: Notice of Applicant Rights Under the Law .Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $116,960 to $160,820.Actual wage offered may vary depending on work location , experience, education, training, external market data, internal pay equity, or other bona fide factors.This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time , and other benefits.