Senior Electrical Engineer (FPGA Design) 1

L3Harris; Camden (NJ); On-site; USD 114,000 - 219,000; Full time

Job summary

L3Harris is seeking a SrASIC/FPGA VHDL Design Engineer in Camden, NJ. This role involves designing and implementing FPGA solutions for defense applications, requiring a strong background in VHDL and FPGA design, along with excellent communication skills. The position offers competitive compensation and a range of benefits, including health insurance and a 401(k) match.

Benefits

Health and disability insurance

401(k) match

Flexible spending accounts

Education assistance

Parental leave

Paid time off

Company-paid holidays

Qualifications

• 3-5+ years’ experience designing FPGA products with VHDL.
• Experience with Xilinx FPGAs and Vivado.
• Active DoD Security Clearance.

Responsibilities

• Derive FPGA design specifications from system requirements.
• Develop detailed FPGA architecture for implementation.
• Validate design through HW/SW integration test.

Skills

VHDL

FPGA design

Good written skills

Good verbal skills

Good presentation skills

Education

Bachelor of Science (BS)

Masters (MS)

PhD

Tools

Vivado

Xilinx FPGAs

Mentor EDA

Job description

L3Harris is dedicated to recruiting and developing high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers’ mission and quest for professional growth. L3Harris provides an inclusive, engaging environment designed to empower employees and promote work-life success. Fundamental to our culture is an unwavering focus on values, dedication to our communities, and commitment to excellence in everything we do.

L3Harris Technologies is the Trusted Disruptor in the defense industry. With customers’ mission-critical needs always in mind, our employees deliver end-to-end technology solutions connecting the space, air, land, sea and cyber domains in the interest of national security.

Job Title: SrASIC/FPGA VHDL Design Engineer

Job Code: 24260

Job Location: Camden, NJ-relocation available for those that qulify

Schedule: 9/80 Regular with every other Friday off

Job Description:

Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design team, responsible for the delivery of FPGAs for defense applications. S/he will architect, implement FPGA design, with hands on design/debug with primarily Ethernet, I2C, SPI, AXI protocols.

L3Harris has state-of-the-art EDA flows/methodologies including Mentor EDA: Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus). We are a learning organization and have the capability to target all FPGA vendors and have ASIC front end capability, with mature design processes.

This is a high impact role in the organization to ensure robust quality and delivery of communication products for National Security.

Essential Functions:

• Derive FPGA design specifications from system requirements
• Develop detailed FPGA architecture for implementation
• Implement design in RTL (VHDL) and perform module level simulations
• Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA)
• Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC) , Static Formal EDA
• Generate verification test plans and perform End to End Simulations
• Support Board, FPGA bring up
• Validate design through HW/SW integration test with test equipment
• Support product collateral for NSA certification

Qualifications:

• Bachelor of Science (BS) -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science)
• 3-5+ years’ experience designing FPGA products with VHDL
• Experience with Xilinx FPGAs and Vivado
• Experience with Revision control system
• Experience with Earned Value Management (EVM)
• Good written, verbal, and presentation skills
• Active DoD Security Clearance

Preferred Additional Skills:

• Experience with mapping algorithms to architecture
• Experience in C++ (OOP)
• Experience with any of protocols : Ethernet, TCP/IP, PCIe, NVMe, USB
• Experience with Xilinx SoC design with SDKs and PetaLinux OS
• Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult

In compliance with pay transparency requirements, the salary range for this role is $114,860-$218,034. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.

#LI-JV1

L3Harris Technologies is proud to be an Equal Opportunity Employer. L3Harris is committed to treating all employees and applicants for employment with respect and dignity and maintaining a workplace that is free from unlawful discrimination. All applicants will be considered for employment without regard to race, color, religion, age, national origin, ancestry, ethnicity, gender (including pregnancy, childbirth, breastfeeding or other related medical conditions), gender identity, gender expression, sexual orientation, marital status, veteran status, disability, genetic information, citizenship status, characteristic or membership in any other group protected by federal, state or local laws. L3Harris maintains a drug-free workplace and performs pre-employment substance abuse testing and background checks, where permitted by law.

Please be aware many of our positions require the ability to obtain a security clearance. Security clearances may only be granted to U.S. citizens. In addition, applicants who accept a conditional offer of employment may be subject to government security investigation(s) and must meet eligibility requirements for access to classified information.

By submitting your resume for this position, you understand and agree that L3Harris Technologies may share your resume, as well as any other related personal information or documentation you provide, with its subsidiaries and affiliated companies for the purpose of considering you for other available positions.

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