Senior DV Engineer — Global Customer Enablement

proteanTecs; Santa Clara, Northern (CA, KY); Hybrid; USD 140,000 - 190,000; Full time

Job summary

proteanTecs is seeking a Senior Design Verification Engineer to join a global team of Application Engineers. You will own advanced DV flow development, debug RTL and gate-level issues, and guide customers through integration of proteanTecs IP.

Join a cutting-edge startup impacting data centers, automotive, and consumer electronics, using ML and analytics to monitor chip health. You will collaborate across regions, drive adoption, and help shape the product roadmap with customer insights.

Qualifications

• Bachelor’s or Master’s degree in electrical/computer engineering, or related field with 3+ years of experience.
• 3+ years hands-on experience with advanced DV flow development and integration.
• Proficiency in SystemVerilog / UVM.
• Advanced testbench architecture development.
• Flow automation and deployment.
• Experience debugging RTL, gate-level, and test-related issues.
• Strong debugging and problem-solving skills.
• Strong foundation in digital design, SoC architecture, and silicon development flows.

Responsibilities

• Customer enablement and technical support.
• Serve as a primary technical interface for proteanTecs customers (Focus North America).
• Support customers with integration of proteanTecs IP and DV flow into customer environments.
• Reproduce customer issues and drive resolution with R&D teams.
• Help customers correlate pre-silicon verification results with post-silicon behavior.
• Create and maintain Application notes and Integration guides.
• Provide structured feedback to R&D and Product Management.
• Participate in feature validation and early access programs.
• Influence product roadmap with customer insights.

Skills

Strong customer-facing communication

Problem-solving

Multitasking

Cross-functional collaboration

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

SystemVerilog / UVM

Advanced Testbench architecture development

Flow automation and deployment

RTL/gate-level debugging

SoC/digital design knowledge

Job description

proteanTecs is seeking a Senior Design Verification Engineer to join a global team of Application Engineers. You will own advanced DV flow development, debug RTL and gate-level issues, and guide customers through integration of proteanTecs IP.

Join a cutting-edge startup impacting data centers, automotive, and consumer electronics, using ML and analytics to monitor chip health. You will collaborate across regions, drive adoption, and help shape the product roadmap with customer insights.