Senior DSP Engineer - End-to-End Modem & SDR Architect

Northwoodspace; Torrance, Northern (CA, KY); Hybrid; USD 140,000 - 180,000; Full time

Job summary

Northwood Space in Torrance, CA is seeking a Senior DSP Engineer to own modem algorithms end-to-end for a next-generation satellite ground network platform. You will define waveform chains and implement them on an in-house SDR/FPGA, collaborating with RF, FPGA, and systems teams.

This role requires translating signal-processing theory into robust, testable code while balancing performance with hardware constraints.

Qualifications

• Bachelor's degree in electrical/computer engineering or related field with 5+ years of relevant experience.
• Experience developing modems or waveform processing chains for SDR, wireless comms, radar, or RF systems.
• Strong understanding of digital communications theory: CCSDS waveforms, BPSK/QPSK/OQPSK, DVB-S2, carrier synchronization, pulse shaping, equalization, and Doppler effects.

Responsibilities

• Own the definition and development of modem algorithms end-to-end, from requirements through implementation and validation.
• Define waveform processing chains—synchronization, pulse shaping, equalization—for SDR/FPGA implementation.
• Partition and implement modem signal-processing across FPGA logic and embedded/host compute within the existing hardware platform.
• Collaborate with RF, FPGA, and systems engineers to integrate modem algorithms and validate performance.
• Develop and run communication system tests to characterize modem performance under realistic channel impairments.

Skills

DSP engineering

Waveform processing

Digital communications

C++

Rust

FPGA

GNU Radio

System testing

Beamforming / radar (EW)

Education

Bachelor's degree in EE/CE

Tools

GNU Radio

Job description

Northwood Space in Torrance, CA is seeking a Senior DSP Engineer to own modem algorithms end-to-end for a next-generation satellite ground network platform. You will define waveform chains and implement them on an in-house SDR/FPGA, collaborating with RF, FPGA, and systems teams.

This role requires translating signal-processing theory into robust, testable code while balancing performance with hardware constraints.