Senior DRAM Security Test Engineer

Micron Technology, Inc; Boise (ID); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Paid time off

Paid holidays

Income protection programs

Job summary

Micron Technology, Inc. seeks a Senior DRAM Security Test Engineer to design and maintain security validation infrastructure for memory products, blending FPGA development, software engineering, AI tools, automation, and memory architecture expertise.

You will collaborate with product security researchers, DRAM architects, and development teams to validate threat-informed mitigations, run large campaigns, and scale platforms for rapid evaluation of emerging threats.

Qualifications

• BS in Electrical Engineering, Computer Engineering, or related field.
• Proven experience with FPGA build using Verilog, SystemVerilog, or VHDL.
• Skilled in FPGA development environments including Xilinx Vivado or Intel Quartus.
• Strong software development skills in Python and/or C++.
• Experience with hardware/software integration and automation.
• Understanding of digital build, memory systems, and test methodologies.
• Excellent debugging, problem-solving, and documentation skills.
• Experience working with Claude or comparable AI-supported software development tools to speed up coding, debugging, automation, test generation, and documentation.

Responsibilities

• Design, develop, and maintain advanced security-focused DRAM test infrastructure.
• Develop FPGA-based platforms with high timing precision and throughput.
• Build software frameworks, automation systems, and execution pipelines.
• Use AI-assisted tools to accelerate development, RTL generation, debugging, and documentation.
• Create workflows for prototyping, characterization, and deployment of new methodologies.
• Develop test capabilities for memory disturbance mechanisms, attack surfaces, and mitigation behavior.
• Integrate host software, FPGA platforms, PCIe interfaces, and DRAM subsystems into scalable environments.
• Collaborate with product security researchers and DRAM architects on threat-informed validation strategies.
• Analyze large validation campaigns and automate triage, insights, and root-cause analysis.

Skills

Python

C++

AI-assisted development

Education

BS in Electrical Engineering or Computer Engineering

Tools

Verilog

SystemVerilog

VHDL

Xilinx Vivado

Intel Quartus

Claude

Job description

Senior DRAM Security Test Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Senior DRAM Security Test Engineer develops advanced security validation infrastructure used to assess the resilience, robustness, and effectiveness of security mitigations in modern memory products. This role combines FPGA development, software engineering, AI‑assisted development, automation, and memory architecture expertise to create scalable platforms capable of accomplishing complex DRAM validation and characterization workloads.

Responsibilities

• Design, develop, and maintain advanced security‑focused DRAM test infrastructure employed to verify memory resilience, mitigation effectiveness, and security‑relevant behaviors.
• Develop FPGA‑based platforms capable of accomplishing complex DRAM command sequences with nanosecond‑level timing precision and high‑throughput operation.
• Build software frameworks, automation systems, and execution pipelines that translate high‑level security test objectives into hardware‑executable workloads.
• Use AI‑assisted development tools such as Claude and other LLMs to speed up software development, RTL generation, debugging, automation, test creation, and technical documentation.
• Develop tools and workflows that support quick prototyping, characterization, and deployment of new security validation methodologies.
• Create security‑focused test capabilities used to evaluate memory disturbance mechanisms, attack surfaces, mitigation behavior, fault conditions, and adversarial access patterns.
• Integrate host software, FPGA platforms, PCIe interfaces, and DRAM subsystems into scalable validation environments supporting large characterization and analytics campaigns.
• Partner with Product Security researchers, DRAM architects, and development teams to develop threat‑informed validation strategies and boost security testing effectiveness.
• Analyze results from large‑scale validation campaigns and develop automated workflows that improve triage, insight generation, root‑cause analysis, and reporting.
• Drive continuous improvements in platform scalability, maintainability, developer productivity, and test execution efficiency through automation and AI‑enabled engineering practices.
• Document architecture, workflows, development standards, and validation methodologies while providing technical leadership and mentorship across engineering teams.
• Define and complete the roadmap for next‑generation DRAM security test infrastructure, enabling faster evaluation of emerging threats, mitigations, and architectural enhancements.

Minimum Qualifications

• BS in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
• Proven experience with FPGA build using Verilog, SystemVerilog, or VHDL.
• Skilled in FPGA development environments including Xilinx Vivado or Intel Quartus.
• Strong software development skills in Python and/or C++.
• Experience with hardware/software integration and automation.
• Understanding of digital build, memory systems, and test methodologies.
• Excellent debugging, problem‑solving, and documentation skills.
• Experience working with Claude or comparable AI‑supported software development tools to speed up coding, debugging, automation, test generation, and documentation.

Preferred Qualifications

• Experience with DRAM architecture, memory subsystems, or JEDEC protocols.
• Familiarity with ATE, FPGA‑based validation systems, or custom test platforms.
• Established experience in building automated characterization and validation workflows.
• Knowledge of PCIe, AXI, DMA, and high‑performance data movement architectures.
• Experience in improving test coverage, throughput, and validation efficiency through custom tooling and automation.

Job Profile(s)

Firmware Engineer 3

Relocation Level: TBD

Benefits

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays.

Equal Opportunity Statement

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

Application Assistance

For US sites only: Please contact Micron’s People Organization at [e-mail].