Senior Director, ASIC Design Verification

Upscale, Inc.; United States; Vor Ort; USD 305.000 - 308.000; Vollzeit

Zusammenfassung

Upscale, Inc. is seeking a Senior Director, ASIC Design Verification to build and lead a hands-on DV team for networking switch ASICs, Ethernet, UALink, and next-gen interconnect silicon.

The ideal leader stays close to DV implementation, recruits, mentors, and establishes the methodology, infrastructure, and culture needed to achieve first-pass silicon success on ambitious schedules in a fast-moving startup.

Qualifikationen

• 16+ years of progressive experience in ASIC or SoC design verification, including a strong track record as a DV lead on complex networking or data‑center ASICs
• Hands‑on expertise in SystemVerilog, UVM, constrained‑random verification, functional coverage, and assertion‑based verification
• Experience building and growing verification teams from the ground up, including hiring, mentoring, and developing engineers
• Multiple successful tape‑outs with accountability for verification sign‑off and first‑pass silicon outcomes
• Working knowledge of networking protocols and architectures, including Ethernet switching and AI‑scale interconnects such as UALink
• Direct experience verifying Ethernet switch ASICs, network processors, or AI/ML interconnect silicon, including integration of protocol verification IP
• Experience with formal verification, hardware emulation, or verification of chiplets and multi‑die designs
• MS or PhD in Electrical Engineering, Computer Engineering, or a closely related field

Aufgaben

• Own end-to-end verification for Upscale's networking switch ASICs and chiplets.
• Build the DV organization. Define the hiring plan and headcount strategy across chip programs.
• Recruit top verification talent, and mentor engineers into a cohesive, high-performing team.
• Remain deeply hands-on.
• Establish DV methodology and infrastructure, including constrained-random, coverage-driven, assertion-based and formal verification, regression management, and emulation.
• Lead tools and reporting, evaluate verification IP and EDA tools, and communicate status and risks to leadership.

Kenntnisse

SystemVerilog

UVM

Constrained-random

Functional coverage

Assertion-based verification

Tapeouts

Ausbildung

MS/PhD in EE/CE or related

Tools

Formal verification

Hardware emulation

Chiplet/multi-die verification

Jobbeschreibung

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical.Our team is talent-dense andhigh-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

Role Overview

The Senior Director, ASIC Design Verification is a hands-on verification leader responsible for building a design verification (DV) team from the ground up and driving verification closure on Upscale's networking switch ASICs, including Ethernet, UALink, and next-generation scale-up interconnect silicon.

The ideal candidate is deeply technical, stays close to DV implementation, and leads by example. At the same time, this leader will recruit, hire, and mentor a high-caliber verification team, establishing the methodology, infrastructure, and culture needed to achieve first-pass silicon success on ambitious schedules. This role is for someone who thrives at the intersection of hands-on verification engineering and team building in a fast-moving startup environment.

Key Responsibilities

• Own end-to-end verification for Upscale's networking switch ASICs and chiplets. This spans verification planning, testbench development, coverage closure, and tape-out sign-off.
• Build the DV organization. Define the hiring plan and headcount strategy across chip programs. Recruit top verification talent, and mentor engineers into a cohesive, high-performing team.
• Remain deeply hands-on.
• Establish DV methodology and infrastructure. This includes constrained-random and coverage-driven verification, assertion-based and formal verification, regression management, and emulation strategy, all designed for reuse across chip generations.
• Partner across engineering. Work with architecture, design, physical design, firmware, and systems teams to define verification plans, align on sign-off criteria, and drive bugs to closure.
• Lead tools and reporting. Evaluate and adopt verification IP and EDA tools, making build-vs-buy decisions that balance risk, schedule, and engineering effort. Communicate verification status, coverage metrics, and technical risks to senior leadership.

Required Qualifications

• 16+ years of progressive experience in ASIC or SoC design verification, including a strong track record as a DV lead on complex networking or data‑center ASICs
• Hands‑on expertise in SystemVerilog, UVM, constrained‑random verification, functional coverage, and assertion‑based verification
• Experience building and growing verification teams from the ground up, including hiring, mentoring, and developing engineers
• Multiple successful tape‑outs with accountability for verification sign‑off and first‑pass silicon outcomes
• Working knowledge of networking protocols and architectures, including Ethernet switching and AI‑scale interconnects such as UALink
• Preferred Qualifications
• Direct experience verifying Ethernet switch ASICs, network processors, or AI/ML interconnect silicon, including integration of protocol verification IP
• Experience with formal verification, hardware emulation, or verification of chiplets and multi‑die designs
• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a closely related field

$305,000 - $308,000 a year

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us [e-mail]—we’re happy to help. Note: This inbox is only for accommodation requests.