Senior Digital IC Design Engineer, SoC & DSP

Cirrus; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Cirrus Logic in Austin, TX is seeking a Digital Design Engineer to join a cross‑functional team developing high‑performance mixed‑signal ICs used by top consumer brands. You will help bring digital subsystems from concept to production and collaborate with analog, verification, and test teams.

The role emphasizes Verilog RTL design, CDC, timing, synthesis, and complex state machines, with opportunities to influence SoC architecture and post‑silicon validation.

Qualifications

• Degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of relevant digital IC design experience (Bachelor's); more with Master's/PhD.
• Strong Verilog RTL design and digital design flow experience.
• Familiarity with CDC, timing, synthesis, and verification.
• Experience with complex state machines and control logic.

Responsibilities

• Design and implement digital subsystems and IP blocks for mixed‑signal ICs from architecture through tape‑out.
• Develop RTL designs using Verilog and integrate into larger SoC environments.
• Design and verify DSP, control, and data‑path logic, including calibration and state machines.
• Perform functional and integration verification; support UVM‑based verification teams.
• Collaborate with analog, layout, and test teams to ensure robust silicon.

Skills

Verilog RTL design

Digital IC design

Clock domain crossing

Functional verification

Timing constraints

Synthesis

State machines

CMOS VLSI fundamentals

DSP concepts

Team collaboration

Education

Bachelor's in Electrical/Computer Engineering

Master's degree (desirable)

PhD (optional)

Tools

MATLAB

Simulink

Job description

Cirrus Logic in Austin, TX is seeking a Digital Design Engineer to join a cross‑functional team developing high‑performance mixed‑signal ICs used by top consumer brands. You will help bring digital subsystems from concept to production and collaborate with analog, verification, and test teams.

The role emphasizes Verilog RTL design, CDC, timing, synthesis, and complex state machines, with opportunities to influence SoC architecture and post‑silicon validation.