Senior Digital IC Design Architect

Cirrus Logic; Austin (TX); On-site; USD 150,000 - 210,000; Full time

Job summary

Cirrus Logic is seeking a Digital Design Engineer to drive digital subsystems in mixed‑signal ICs, interfacing with analog, verification, layout and test teams. You will contribute to RTL design, verification, and silicon debugging across SoC environments.

The role emphasizes strong Verilog RTL expertise, experience with complex state machines, and collaboration in a fast‑paced development setting. Prior DSP exposure is a plus, with backend flow familiarity.

Qualifications

• Degree in Electrical or Computer Engineering or related.
• 10+ years digital IC design experience with Bachelor's.
• 8+ years with Master's.
• 6+ years with PhD.

Responsibilities

• Design and implement digital subsystems and IP blocks for mixed‑signal ICs from architecture through tape‑out.
• Develop RTL designs using Verilog and support integration into larger SoC environments.
• Design and verify DSP, control, and datapath logic, including calibration and monitoring state machines.
• Perform functional verification, integration verification, and support UVM‑based verification teams.
• Contribute to behavioral and system modeling of digital and mixed‑signal systems.
• Support post‑silicon validation, characterization, and production test, including lab bring‑up and silicon debug.
• Collaborate across disciplines to ensure correct interaction between digital logic and analog circuitry.
• Participate in design reviews, tape‑out readiness, and root‑cause analysis for silicon or system issues.

Skills

Verilog RTL design

Digital design flow

State machines

CMOS VLSI basics

Team-based collaboration

DSP background optional

ARM-based SoCs knowledge

MATLAB/Simulink

Synthesis

Place & route

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree (advantage)

PhD (advantage)

Tools

MATLAB/Simulink

Synthesis tools

Place & Route tools

Verification environments (UVM)

Job description

Cirrus Logic is seeking a Digital Design Engineer to drive digital subsystems in mixed‑signal ICs, interfacing with analog, verification, layout and test teams. You will contribute to RTL design, verification, and silicon debugging across SoC environments.

The role emphasizes strong Verilog RTL expertise, experience with complex state machines, and collaboration in a fast‑paced development setting. Prior DSP exposure is a plus, with backend flow familiarity.