Senior Digital Design Engineer

Hibob Inc.; San Jose (CA); On-site; USD 130,000 - 200,000; Full time

Benefits offered by this job

Discretionary bonus

Equity

Medical benefits

Onsite at San Jose HQ

Job summary

Credo is seeking a Senior PHY RTL Design Engineer to lead RTL architecture, design, and verification of SerDes DSP blocks for next‑gen networking, AI, and data center products. The role is onsite at our San Jose HQ with base salary 130k–200k USD and eligibility for a discretionary bonus, equity, and comprehensive benefits.

Ideal candidates have strong SystemVerilog skills, 5+ years in digital design, and a solid understanding of high‑speed SerDes architectures.

Qualifications

• BS/MS/PhD in Electrical or Computer Engineering.
• 5+ years of digital design experience or equivalent for senior candidates.
• Strong RTL development using SystemVerilog.
• Experience designing high‑speed communication or DSP hardware.
• Fixed-point arithmetic RTL implementation understanding.
• Experience with ASIC development flow (Lint, CDC/RDC, Synthesis, Timing).

Responsibilities

• Define RTL micro‑architecture for digital PHY and SerDes DSP functions.
• Develop synthesizable RTL for DSP blocks (FFE, DFE, adaptive equalization, CDR loops).
• Translate DSP algorithms into RTL with system architects and algorithm teams.
• Optimize designs for performance, power, area, and latency.
• Verify DSP modules and debug functional issues.
• Support synthesis, timing closure, CDC/RDC analysis, and DFT integration.
• Analyze silicon bring‑up data with validation teams to resolve issues.

Skills

SystemVerilog

Digital design

DSP hardware

SerDes

RTL debugging

Python scripting

Education

BS/MS/PhD in Electrical Engineering

Tools

Synopsys EDA

Cadence EDA

Siemens EDA

Job description

Team Credo is looking for a Senior PHY RTL Design Engineer to join our mission to transform connectivity at scale. In this role, you will be responsible for the RTL architecture, design, implementation, and verification of advanced SerDes PHY Digital Signal Processing (DSP) blocks used in next-generation networking, AI, data center, and high-performance computing products. The ideal candidate possesses strong digital design fundamentals, hands‑on RTL development experience, and a good understanding of high‑speed SerDes architecture. This position will be onsite at our San Jose, CA HQ.
Base salary range is $130,000 - $200,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.
Why Credo

• Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
• People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
• Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy-efficient connections around the world – and our team powers new products and markets that come next.

Qualifications

Basic Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of digital design experience (or equivalent expertise for senior candidates).
• Strong RTL development skills using System Verilog.
• Experience designing high-speed communication or DSP hardware.
• Solid understanding of fixed-point arithmetic RTL implementation.
• Experience with ASIC development flow (e.g. Lint, CDC/RDC, Synthesis, Timing analysis).
• Familiarity with EDA tools from Synopsys, Cadence, or Siemens.
• Strong debugging and problem-solving skills.

Preferred Qualifications

• Experience with high-speed SerDes standards such as PCIe, Ethernet.
• Understanding of SerDes receiver and transmitter architectures, and DSP algorithms (e.g. LMS adaptation, timing recovery).
• Familiarity with Python or other scripting languages.
• Understanding of MATLAB or C/C++ modeling.
• Knowledge of mixed-signal PHY architecture and analog/digital interfaces.
• Experience of mixed-signal PHY simulations.
• Experience supporting silicon bring‑up and post-silicon validation.
• Exposure to advanced process nodes (7nm, 5nm, 3nm, or beyond).

Responsibilities

• Define RTL micro‑architecture for digital PHY and SerDes DSP functions.
• Develop synthesizable RTL for DSP blocks (FFE, DFE, adaptive equalization, CDR loops).
• Work with system architects and algorithm teams to translate DSP algorithms into RTL.
• Optimize designs for performance, power, area, and latency.
• Verify DSP modules and debug functional issues.
• Support synthesis, timing closure, CDC/RDC analysis, and DFT integration.
• Analyze silicon bring‑up data with validation teams to resolve issues.
• Support PHY integration and system-level debugging.

About Credo

Credo’s mission is to transform connectivity at scale through fast, reliable, and energy‑efficient system solutions. Our high‑speed copper and optical interconnect products deliver industry‑leading power and performance at up to 1.6T to meet the ever‑expanding data infrastructure demands of AI.
Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.
Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, gender identity, sexual orientation, pregnancy, marital status, national origin, ethnicity, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [e-mail].