Senior Digital Design Engineer

Insight Global; Chandler (AZ); On-site; USD 150,000 - 230,000; Full time

Job summary

Insight Global is seeking a senior engineer to lead digital architecture and PMIC development for automotive and industrial PMICs. You will drive from concept through RTL, silicon validation, qualification, and production release, coordinating with analog, verification, and systems teams to ensure high-quality mixed-signal solutions.

The role requires at least 8 years in digital IC design, strong RTL background, and deep knowledge of EDA flows (Cadence, Synopsys, Siemens).

Qualifications

• Minimum 8 years of experience in digital IC design and development, including technical leadership and architecture responsibilities.
• Strong understanding of digital design fundamentals, clock-domain crossing, reset architecture, and low-power design techniques.
• Expertise in RTL design using Verilog/SystemVerilog for complex digital and mixed-signal ICs.
• Experience with synthesis, static timing analysis, equivalence checking, DFT, and physical implementation flows.
• Strong knowledge of modern verification methodologies, including UVM, assertions, formal verification, and coverage-driven verification.
• Experience developing digital controllers for PMICs, power management systems, automotive electronics, or industrial applications is highly desirable.
• Proficiency with industry-standard EDA tools from Cadence, Synopsys, and Siemens EDA.

Responsibilities

• Lead digital architecture, design, verification, and implementation of PMICs.
• Drive product execution from concept through RTL development, silicon validation, qualification, and production release.
• Collaborate across analog, verification, validation, subsystem, SoC, applications, systems, product definition, and customer-facing teams to deliver high-quality mixed-signal solutions.

Skills

Digital IC design

RTL design

Verification methodologies

UVM

Assertions

Formal verification

Coverage-driven verification

Synthesis

Static timing analysis

Equivalence checking

DFT

Physical implementation flows

PMICs experience

Automotive electronics

Power management systems

EDA tools

Tools

Cadence

Synopsys

Siemens EDA

Job description

Job Description

This role will lead digital architecture, design, verification, and implementation of next-generation Power Management ICs (PMICs) for automotive and industrial applications.

Drive product execution from concept through RTL development, integration, silicon validation, qualification, and production release.

Collaborate across analog, verification, validation, subsystem, SoC, applications, systems, product definition, and customer-facing teams to deliver high-quality mixed-signal solutions.

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment regardless of their race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please send a request to [e-mail] learn more about how we collect, keep, and process your private information, please review Insight Global's Workforce Privacy Policy: https://insightglobal.com/workforce-privacy-policy/.

Skills and Requirements

Minimum 8 years of experience in digital IC design and development, including technical leadership and architecture responsibilities.

Strong understanding of digital design fundamentals, finite state machines, clock-domain crossing, reset architecture, and low-power design techniques.

Expertise in RTL design using Verilog/SystemVerilog for complex digital and mixed-signal ICs.

Experience with synthesis, static timing analysis, equivalence checking, DFT, and physical implementation flows.

Strong knowledge of modern verification methodologies, including UVM, assertions, formal verification, and coverage-driven verification.

Experience developing digital controllers for PMICs, power management systems, automotive electronics, or industrial applications is highly desirable.

Proficiency with industry-standard EDA tools from Cadence, Synopsys, and Siemens EDA.