Senior DFT Architect (remote)

VeroTech; Town of Belgium (WI); Hybrid; USD 120,000 - 150,000; Full time

Benefits offered by this job

Company car

Monthly net allowances

Yearly bonus

Insurances

Meal vouchers

Eco-cheques

Job summary

VeroTech, located in Wisconsin, is seeking a Sr. DFT Architect to implement advanced DFT techniques for complex SoCs. The ideal candidate brings over 10 years of digital ASIC design experience with a focus on DFT insertion. Key responsibilities include defining DFT architecture, managing test modes, and driving implementation of test structures. VeroTech offers a collaborative environment with flexible work options and a comprehensive benefits package including team activities and support for personal development.

Qualifications

• 10+ years in digital ASIC design concentrating on DFT insertion and ATPG.
• Experience guiding DFT flows and mentoring.
• Ability to resolve timing and routing challenges.

Responsibilities

• Define DFT architecture and lead its implementation.
• Manage test modes, timing constraints, and DFT integration.
• Generate and debug ATPG patterns to improve fault coverage.
• Support test engineering on post-silicon validation and debugging.

Skills

DFT experience

Verilog or VHDL proficiency

Knowledge of IC standards

EDA tools experience

TCL and scripting languages

Technical leadership

Education

Master’s degree in electronics or electrical engineering

Tools

Synopsys Fusion Compiler

TestMax

Siemens/Mentor Graphics' Tessent

Job description

Overview

Join VeroTech as a Sr. DFT Architect and become part of our community where innovation and people come first. You’ll take on exciting technical challenges and develop your expertise while creating solutions that drive progress across several industries.

About The Role

As a Sr. DFT Engineer, you’ll be at the forefront of implementing and validating advanced DFT techniques on complex SoCs and subsystems. Your work will directly influence test quality, coverage, and silicon success, from defining test modes and timing constraints to supporting post-silicon validation.

Key responsibilities

• Define DFT architecture and lead its implementation across SoCs and key subsystems.
• Define and manage test modes, timing constraints, and DFT integration.
• Drive implementation of scan-based test, memory test, and on-chip test control structures.
• Generate and debug ATPG patterns to improve fault coverage.
• Collaborate with physical design to resolve timing and routing challenges.
• Support test engineering on (post) silicon validation and debugging.

What we're looking for

We are seeking an senior ASIC designer with solid DFT experience. Ideal candidates will have the following:

• Master’s degree in electronics or electrical engineering with 10+ years in digital ASIC design, focusing on DFT insertion and ATPG.
• Recent technical leadership & mentoring experience guiding DFT flows and methodology.
• Proficiency in Verilog or VHDL for test logic development.
• Strong knowledge in IC standards like IEEE 1149.1, 1149.6, and 1687 (IJTAG) for testing & manufacturability.
• Hands-on experience with advanced EDA tools like Synopsys Fusion Compiler + TestMax or Siemens/Mentor Graphics' Tessent.
• Proficiency in TCL and other scripting languages like Python & Shell.
• If you work remotely, you're open to fly in 1 week per month.

At VeroTech, you’re part of a real community where engineers grow and thrive together while working on cutting-edge projects in several sectors, enjoying flexibility and true support from colleagues. We offer personalized career development tailored to your ambitions, hybrid work options, and a strong focus on learning and growth. You’ll enjoy regular teambuilding activities in a collaborative environment, along with a broad salary package that includes a company car, monthly net allowances, a yearly bonus, insurances, meal vouchers and eco-cheques.

More than just shaping technology, at VeroTech we're shaping the future. Are you ready to shape yours?

Ready to inspire?

Apply now and take the next step in your career. Let’s build the future together!