Senior Design Verification Engineer Satellite Communications

Amazon; San Diego (CA); On-site; USD 159,000 - 215,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Amazon Kuiper Manufacturing Enterprises LLC seeks a verification engineer to define and implement SOC verification environments for pre- and post-silicon testing, focusing on high-speed interfaces and embedded processors. The role involves developing test plans, running regressions, and triaging failures within a cutting-edge CMOS/CMOS-generation context.

The candidate will collaborate with antenna and communications teams to ensure robust IP and subsystem validation, leveraging UVM, SystemC,

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering.
• 3+ years of UVM, C, System C, and scripting experience.
• 7+ years in verification preferably in communication systems.

Responsibilities

• Implement a state of the art verification environment for IP, subsystem and SOC to facilitate testing of the DUT against reference models.
• Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
• Understand and debug system level communication scenarios on pre silicon and post silicon environments.
• Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C
• Develop a highly automated environment to triage regression fails and report issues to stake holders.

Skills

UVM

C

SystemC

scripting

AI/LLM tools

Education

Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering

Tools

Matlab

SystemC

Job description

Amazon Kuiper Manufacturing Enterprises LLC seeks a verification engineer to define and implement SOC verification environments for pre- and post-silicon testing, focusing on high-speed interfaces and embedded processors. The role involves developing test plans, running regressions, and triaging failures within a cutting-edge CMOS/CMOS-generation context.

The candidate will collaborate with antenna and communications teams to ensure robust IP and subsystem validation, leveraging UVM, SystemC,