Senior Design Verification Engineer (remote position)

Correct Designs; Austin (TX); Hybrid; USD 90,000 - 140,000; Full time

Job summary

An established industry player is seeking a Senior Design Verification Engineer to tackle exciting challenges in hardware development. This role offers the unique blend of contract flexibility and long-term stability, allowing you to work on cutting-edge projects in AI, machine learning, and more. As part of a respected team, you'll engage in verifying advanced CPU/GPU-based SOCs and contribute to innovative solutions in various domains. Enjoy the freedom of both in-person and remote work options while being supported by comprehensive healthcare and retirement benefits. Join a collaborative environment where your expertise will make a significant impact!

Benefits

Healthcare benefits

Retirement benefits

Flexible work options

Long-term contract opportunities

Generous hourly rates

Qualifications

• 8+ years of verification experience in hardware development.
• Strong background in SystemVerilog and UVM methodologies.

Responsibilities

• Verify complex design blocks using advanced SV/UVM verification environments.
• Develop and execute pre-silicon verification test plans.
• Create directed and random verification tests to validate functionality.

Skills

SystemVerilog

UVM methodologies

Debug tools (DVE/Verdi)

Object-Oriented programming

Computer architecture

Data structures

Analytical skills

Problem-solving skills

Interpersonal skills

Communication skills

Education

Bachelor's degree in Electrical Engineering

Master's degree in Computer Engineering

Master's degree in Computer Science

Tools

Perl

Ruby

Make

Job description

Senior Design Verification Engineer

Looking for new challenges? Would you like the variety of a contract position along with long-term stability and benefits? Correct Designs can give it all to you.

Correct Designs is currently seeking talented Verification Engineers with prior SystemVerilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC products for vision processing, aerospace FPGAs, medical electronics, RISC-V based SoC, ARM-based peripherals, and mixed signal DSPs. Successful candidates will support verification of advanced CPU/GPU based SOCs.

Correct Designs is NOT the typical contracting, staff augmentation firm. Our engineers have respected long-term roles with generous hourly rates in excellent team environments. A typical contract may last 3 years, though shorter and longer-term work is available. We are well respected in the Design Verification community, with clients always seeking new CDI engineers. If you need a few months off between contracts, you can take that break and know there will be plenty of work when you return. For those seeking stability, moving to the next contract is straightforward. Correct Designs also provides healthcare and retirement benefits.

We are based in Austin, Texas, with clients throughout the US. Opportunities for both in-person and remote work are available.

Our current positions are filled, but we have clients looking for skilled CDI engineers regularly. Please submit your resume so we can match you with upcoming projects.

Whether you are an experienced veteran seeking new challenges or a talented engineer looking to broaden your experience, we offer exciting career options.

Responsibilities:

• Verify complex design blocks using advanced SV/UVM verification environments
• Develop and execute pre-silicon verification test plans
• Create directed and random verification tests to validate block and IP functionality
• Develop verification components and tools
• Implement verification functional coverage using industry-standard tools and methods
• Debug regression failures
• Replicate functional issues in external or post-silicon environments; review and enhance tests to verify bug fixes

Required Skills and Experience:

• 8+ years of proven verification experience in hardware development
• Strong background in SystemVerilog and UVM methodologies
• Proficiency with debug tools such as DVE/Verdi
• Experience with Object-Oriented programming, computer architecture, and data structures
• Strong analytical and problem-solving skills with keen attention to detail
• Excellent interpersonal and communication skills
• Comfortable working across geographies

Desired Skills:

• Experience architecting/developing verification environments and infrastructure, including scripting with Perl, Ruby, Make, or similar
• Experience in related domains such as formal verification, RTL design, or software development

Education:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science