Senior Design Verification Engineer (eInfochips Inc)

Arrow Enterprise Computing Solutions; United States; On-site; USD 100,000 - 140,000; Full time

Benefits offered by this job

Medical, Dental, Vision Insurance

401k with Matching Contributions

Disability Insurance

Health Savings Account (HSA) Options

Paid Time Off

Tuition Reimbursement

Growth Opportunities

Job summary

Arrow Enterprise Computing Solutions is seeking an experienced verification engineer to build scalable testbenches using UVM and SystemVerilog. The role focuses on constrained-random testing, coverage closure, and gate-level verification to ensure robust power-up and timing behavior.

You will plan verification from architectural specs, automate regression runs, and work with Cadence Xcelium or other major simulators.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong DV fundamentals and verification methodologies.
• Experience with constrained-random verification and assertions (SVA).
• Knowledge of AMBA AXI/AHB/APB protocols preferred.

Responsibilities

• Testbenches: Build scalable verification environments using UVM and SystemVerilog.
• Planning: Create detailed verification plans from architectural specifications.
• Execution: Write, run, and debug constrained-random and directed tests.
• Coverage: Define, measure, and close functional and code coverage metrics.
• Gate-Level: Run gate-level simulations to verify power-up and timing states.
• Automation: Develop scripts to automate regression runs and triage failures.

Skills

DV fundamentals

MMU verification

SRAM/memory subsystem verification

AXI bus protocols

DSP verification

Education

Bachelor's or Master's in EE/CE or related field

Tools

Cadence Xcelium

Synopsys VCS

Siemens Questa

Job description

What You'll Be Doing:

• Testbenches: Build scalable verification environments using UVM and SystemVerilog.
• Planning: Create detailed verification plans from architectural specifications.
• Execution: Write, run, and debug constrained-random tests and directed tests.
• Coverage: Define, measure, and close functional and code coverage metrics.
• Gate-Level: Run gate-level simulations to verify power-up and timing states.
• Automation: Develop scripts to automate regression runs and triage failures.

What We Are Looking For:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Languages: Strong proficiency in SystemVerilog and scripting (Python, Perl, or Tcl).
• Methodology: Hands‑on experience with UVM (Universal Verification Methodology)
• Tools: Experience with industry-standard simulators Cadence Xcelium preferred, but experience with Synopsys VCS, or Siemens Questa will translate
• Concepts: Deep understanding of constrained-random verification, assertions (SVA), and functional coverage.
• Protocols: Knowledge of common protocols like AMBA (AXI/AHB/APB)

Preferred Qualifications:

• Experience with formal verification tools and methodologies.
• Background in power‑aware verification using UPF/CPF.
• Experience verifying custom ARM or DSP processor cores.
• Familiarity with emulation platforms like Palladium.
• Experience with: MMU verification
• SRAM/ memory subsystem verification
• Nice‑to‑have: DSP verification experience
• Modeling (RNM / behavioral models)

Scope of Work:

• Verification at system/subsystem level, using SV/UVM + C-based testing, with emulation (Cadence Palladium).
• New co‑processing subsystem (with NPU, MMU, SRAM, AXI).
• Memory subsystem interactions
• DSP/signal processing
• SystemVerilog + UVM-based verification
• C-based test development (processor‑in‑loop simulation)
• Use of emulation platforms (Cadence Palladium or similar)
• Some modeling using Real Number Models (RNM) for analog/digital interaction

Key Skills Needed:

• Strong DV fundamentals
• Experience with: MMU verification
• SRAM/memory subsystem verification
• Bus protocols (AXI)
• Nice‑to‑have: DSP verification experience
• Modeling (RNM / behavioral models)

What's In It for You:

• Medical, Dental, Vision Insurance
• 401k, With Matching Contributions
• Short-Term/Long-Term Disability Insurance
• Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
• Paid Time Off (including sick, holiday, vacation, etc.)
• Tuition Reimbursement
• Growth Opportunities
• And more!

Work Arrangement:

Fully OnSite: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.

Location:

Complete On-Site at Minneapolis, MN (Preferred)/ Phoenix, AZ

About eInfochips:

eInfochips, an Arrow company (Fortune #154), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow's $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow's Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across various industries & verticals.

EEO Statement:

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)

Location:

US-MN-Minnesota (Remote Employees)

Remote Work Information:

Remote work employees may be required to be present at the closest designated Arrow office for work-related purposes, at the Company's request and sole discretion.

Time Type:

Full time

Job Category:

Engineering Services