Senior Design Verification Engineer

Intel Corporation; Austin (TX); On-site; USD 191,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health insurance

Retirement plan

Paid time off

Job summary

Intel Corporation in Austin, TX is seeking an IP Design Verification Engineer to ensure IP functionality and reliability. You will collaborate across architecture, design, and verification teams to deliver cutting-edge IPs for next-generation products.

This role emphasizes building verification environments with SystemVerilog and UVM, conducting system simulations, debugging presilicon issues, and documenting verification plans. On-site role with competitive compensation and growth opportunities.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 9+ years in IP functional verification with relevant degree.
• Hands-on experience building verification environments using SystemVerilog and UVM.
• Expertise in RTL design and debugging with standard tools.

Responsibilities

• Develop and execute verification plans to ensure IP logic meets microarchitecture specs.
• Create and maintain test benches and verification environments for high coverage.
• Perform system simulations to verify designs, analyze power and timing, and identify bugs presilicon.
• Debug verification issues by root-causing and implementing corrective measures.
• Collaborate with architects, RTL developers, and physical design teams to enhance verification methodologies.
• Document verification plans and drive technical reviews.
• Maintain and improve verification infrastructure, tools, and methodologies.
• Contribute to development of verification infrastructure and TFMs.

Skills

SystemVerilog

UVM

RDMA networking IP verification

Python scripting

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

RTL debugging tools

Job description

About the Role

As an IP Design Verification Engineer, you will play a critical role in shaping Intel's innovations by ensuring the functionality and reliability of our intellectual property (IP) designs. You will join a dynamic team that collaborates across architecture, design, and verification groups to ensure our solutions meet and exceed industry standards. Your work will directly impact the development of groundbreaking technologies, driving Intel's success in delivering world-class products to the market. This is an exciting opportunity to contribute to cutting-edge projects while advancing your career in a forward-thinking and collaborative environment.

Key Responsibilities

• Develop and execute comprehensive verification plans to ensure IP logic meets microarchitecture specifications
• Create and maintain test benches and verification environments to achieve high coverage and reliability
• Perform system simulations to verify designs, analyze power and timing, and identify bugs in the presilicon environment
• Debug verification issues by replicating, root-causing, and implementing corrective measures for failing tests
• Collaborate with architects, RTL developers, and physical design teams to enhance verification methodologies for complex features
• Document verification plans and drive technical reviews with architecture and design teams
• Maintain and improve existing verification infrastructure, tools, and methodologies
• Participate in defining verification infrastructure and contribute to the development of technical flow methodologies (TFMs)

You Should Demonstrate the Following to Be Successful

• Strong collaboration and communication skills to effectively work across architecture, design, and physical teams
• Demonstrated ability to lead technical reviews and drive alignment on verification strategies
• Passion for continuous learning, innovation, and contributing to a culture of technical excellence
• Proven ability to analyze and resolve complex design issues in a presilicon environment

Minimum Qualifications

• Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field
• 9+ years of experience in IP functional verification with a Bachelor's degree, 6 years with a Master's degree, or 4 years with a PhD
• The above experience must include: Hands-on experience in building verification environments using SystemVerilog and UVM
• Expertise in RTL design and debugging using industry-standard tools and methodologies
• Hands-on experience verifying networking IPs/SoCs implementing RDMA (RoCEv2, iWARP, InfiniBand) or comparable reliable transport protocols (e.g., Ultra Ethernet Transport, TCP offload), including features such as QP/connection state, retransmission, packet ordering, and congestion control

Preferred Qualifications

• Familiarity with scripting languages, such as Python or Perl, to automate verification tasks

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, Texas, Austin

Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara

Position of Trust: N/A

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD

Work Model for this Role

This role will require an on-site presence.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance.

Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.