Senior Debug Verification Engineer

Altera Corporation; San Jose, Northern (CA, KY); Hybrid; USD 149,000 - 215,000; Full time

Job summary

Altera Corporation in San Jose, California, is seeking a Sr. Debug Design Verification Engineer to lead pre-silicon verification for SoC, FPGA and full-chip designs, and to develop test cases and UVM testbenches.

The role requires defining verification strategies and coordinating with Design, SW and Architecture teams to achieve full coverage. Responsibilities include pre-silicon verification, testbench creation, and debugging architecture (JTAG, USB, PCIe).

Qualifications

• 8+ years of experience with complex ASIC designs and/or verification.
• 8+ years of SystemVerilog language experience.
• 8+ years of experience on UVM verification methodology, and formal verification method.
• 8+ years of scripting in Linux/Unix environments, with Perl and/or Python desirable.
• Strong communication skills and ability to work with a team spread across different geography sites.

Responsibilities

• Pre-silicon system verification for SoC, FPGA, and full-chip designs.
• Create test cases and testbenches using UVM.
• Define verification strategies, methodology and test plans for full coverage.
• Coordinate cross-functional efforts with Design, SW, and Architecture teams to achieve full coverage.
• Experience with Design for Debug (JTAG, High-speed USB, PCIe) architectures; Emulation experience is a plus.

Skills

SystemVerilog

UVM

ASIC verification

Testbench development

Emulation

Tools

Linux/Unix scripting

Perl

Python

Emulation tools

Debug architectures

Job description

## **Job Description:****About Altera**At AlteraTM, our independence as the world’s largest pure‐play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‐leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.**About the Role**As a **Sr. Debug Design Verification Engineer**, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls.**Key Responsibilities:*** Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification.* Create testcase and testbench with UVM methodology* Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification* Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.* Experience with ARM and RISC Debug Architectures is desired with focus on design verification.* Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.* Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan* Experience on Emulation will be an add on.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. **$149,100 - $215,000 USD**We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.#MD-1### ## **Qualifications:****Minimum Qualifications*** 8+ years of experience with complex ASIC designs and/or verification* 8+ years of experience with SystemVerilog language* 8+ years of experience on UVM verification methodology, and formal verification method* 8+ years of experience scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable.* Strong communication skills and the ability to work with a team spread across different geography sites### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.