Senior Cyber FPGA Design Verification Engineer

ZipRecruiter; Dedham (MA); On-site; USD 150,000 - 190,000; Full time

Job summary

Join a forward-thinking company as a Senior Cyber FPGA Design Verification Engineer, where you will play a crucial role in product design from architecture to production. This position offers you the chance to work with cutting-edge technology in a collaborative environment, focusing on secure product development for national security. You will leverage your expertise in design verification methodologies and scripting languages to create efficient test plans and simulation environments. Enjoy a flexible schedule, competitive benefits, and opportunities for continuous learning while making a significant impact in the field.

Benefits

401k matching

Flex time off

Paid parental leave

Healthcare

Wellness programs

Employee resource groups

Flexible schedules

Qualifications

• Experience defining verification methodology for complex FPGAs.
• Ability to analyze requirements and create test plans.

Responsibilities

• Member of a cross-functional team responsible for product design.
• Develop scalable simulation environments using SystemVerilog/UVM.

Skills

OVM / UVM design verification methodology

Scripting languages (bash/csh, Perl, TCL, Python)

VHDL or similar hardware description languages

Education

Bachelor’s degree

Tools

SystemVerilog

Xilinx FPGA

Questa Advanced Functional Verification tools

Job description

Job Description: Senior Cyber FPGA Design Verification Engineer
Location: Dedham, MA
Salary: Up to $190,000 yearly
Type: Direct Placement
Sign-on Bonus: $3,000
RELOCATION ASSISTANCE AVAILABLE

As a Senior Cyber FPGA Design Verification Engineer, you will be a member of a cross-functional team responsible for product design, from system architecture & requirements allocation through product release and production of cost-sensitive secure products.

We encourage you to apply if you have experience with:

• OVM / UVM design verification methodology
• Scripting languages such as bash/csh, Perl, TCL, Python, or similar
• VHDL or similar hardware description languages

What sets you apart:

• Experience defining verification methodology for complex FPGAs
• Ability to analyze requirements, create test plans, and build scalable simulation environments using SystemVerilog/UVM
• Familiarity with testing complex designs, code coverage, functional coverage, assertions
• Ability to work in a dynamic environment with changing needs and requirements
• FPGA/ASIC design experience is a plus
• Familiarity with Xilinx FPGA & Questa Advanced Functional Verification tools is a plus
• Team player who thrives in collaborative environments and celebrates team success

Our Commitment to You:

• Opportunities for continuous learning and development
• Research-oriented work with award-winning teams developing practical solutions for national security
• Flexible schedules, including every other Friday off (9/80 schedule)
• Competitive benefits: 401k matching, flex time off, paid parental leave, healthcare, wellness programs, employee resource groups, and more

Minimum Requirements:

• Bachelor’s degree
• Secret clearance
• Willingness to travel occasionally

We are an EOE. If interested, please contact: Thomas Masters at 866-868-4473 Ext. 212 or [e-mail]