Senior CPU Architect: High-Performance Microarchitecture

AheadComputing Inc.; Portland (OR); On-site; USD 120,000 - 180,000; Full time

Job summary

AheadComputing Inc. in Portland, OR, is seeking a talented performance modeling engineer to shape the next generation of high-performance processors.

You will define features to hit performance, power, area, and timing targets, and prototype them through experiments. You will collaborate with design and verification teams to refine microarchitecture, write high-level architecture specs, and validate that RTL designs meet expected performance under real workloads.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, CS, or related field with 4+ years of experience.
• Master’s degree with 3+ years or PhD with 1+ years is acceptable.
• Strong analytical and programming skills in C++ and Python.

Responsibilities

• You will innovate and define features to target performance, power, area, and timing goals.
• You will propose and prototype features, run experiments, and analyze trade-offs between different implementation strategies.
• You will partner with design and verification engineers to develop microarchitecture, and write high-level architecture specifications.
• You will explore high performance strategies and validate that the RTL design meets targeted performance.

Skills

Out-of-order microarchitecture

Performance model development

C++ (OO) programming

Python scripting

Problem-solving

Memory coherence

Multi-core architectures

RISC-V familiarity

Education

Bachelor’s degree in Electrical/Computer Engineering, CS, or related field

Job description

AheadComputing Inc. in Portland, OR, is seeking a talented performance modeling engineer to shape the next generation of high-performance processors.

You will define features to hit performance, power, area, and timing targets, and prototype them through experiments. You will collaborate with design and verification teams to refine microarchitecture, write high-level architecture specs, and validate that RTL designs meet expected performance under real workloads.