Server Performance Architect: Next-Gen CPU Optimization

Advanced Micro Devices; Austin (TX); On-site; USD 170,000 - 260,000; Full time

Benefits offered by this job

AMD benefits

Job summary

Advanced Micro Devices in Austin, TX is seeking an accomplished Server Systems Performance Architect to lead performance verification for next‑gen server CPUs. You will architect, validate, and optimize through full chip simulation and emulation platforms, driving data‑driven decisions to maximize throughput and minimize latency.

The role requires deep expertise in CPU microarchitecture, performance modeling, and cross‑functional collaboration with architecture, RTL, software, and firmware

Qualifications

• 15+ years in performance modeling and verification.
• Proven leadership of cross-functional engineering teams.
• Familiarity with PMC DV, latency and throughput validation, emulation platforms, and performance debug flows.
• Deep understanding of x86 ISA, microarchitecture, and performance metrics.
• Experience with performance test suites and simulation infrastructure.

Responsibilities

• Lead and mentor a high-performing verification team.
• Define and execute verification strategy for high-performance x86 CPU cores.
• Collaborate with architecture, RTL, performance modeling, and firmware teams to validate KPIs.
• Analyze performance bottlenecks via simulation, emulation, and silicon data.
• Advance AI/ML-based infrastructure for performance analysis and anomaly detection.

Skills

Performance verification

CPU microarchitecture

Data-driven mindset

Leadership

Cross-functional collaboration

Education

MS/PhD in Computer Engineering

Tools

cycle-accurate simulators

emulators

Performance counters

Job description

Advanced Micro Devices in Austin, TX is seeking an accomplished Server Systems Performance Architect to lead performance verification for next‑gen server CPUs. You will architect, validate, and optimize through full chip simulation and emulation platforms, driving data‑driven decisions to maximize throughput and minimize latency.

The role requires deep expertise in CPU microarchitecture, performance modeling, and cross‑functional collaboration with architecture, RTL, software, and firmware